单周期CPU-verilog语言

Alu.vmoduleALU(aluControl,a,b,result,zero);input[3:0]aluControl;input[31:0]a,b;outputzero;output[31:0]result;reg[31:0]result;always@(aluControloraorb)begincase(aluControl)4'b0000:result=a&b;4'b0001:result=a|b;4'b0010:result=a+b;4'b0110:result=a-b;4'b0111:result=(ab)?1:0;endcaseendassignzero=(result==0)?1:0;endmoduleALUcontrol.vmoduleALUcontrol(aluop,funct,aluControl);input[1:0]aluop;input[5:0]funct;outputreg[3:0]aluControl;always@(*)begincase(aluop)2'b00:aluControl=4'b0010;2'b01:aluControl=4'b0110;2'b10:begincase(funct)6'b100000:aluControl=4'b0010;6'b100010:aluControl=4'b0110;6'b100100:aluControl=4'b0000;6'b100101:aluControl=4'b0001;6'b101010:aluControl=4'b0111;default:aluControl=4'b0010;endcaseenddefault:aluControl=4'b0010;endcaseendendmoduleCtrl.vmodulecontrolUnit(instruction,zero,RegDst,Jump,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUsrc,RegWrite);input[5:0]instruction;inputzero;outputregRegDst;outputregJump;outputregBranch;outputregMemRead;outputregMemtoReg;outputreg[1:0]ALUOp;outputregMemWrite;outputregALUsrc;outputregRegWrite;always@(*)begincase(instruction)6'b000000://RtypebeginRegDst=1;ALUsrc=0;MemtoReg=0;RegWrite=1;MemRead=0;MemWrite=0;Branch=0;ALUOp[1]=1;ALUOp[0]=0;Jump=1;end6'b001000://addibeginRegDst=0;ALUsrc=1;MemtoReg=0;RegWrite=1;MemRead=0;MemWrite=0;Branch=0;ALUOp[1]=1;ALUOp[0]=0;Jump=1;end6'b100011://lwbeginRegDst=0;ALUsrc=1;MemtoReg=1;RegWrite=1;MemRead=1;MemWrite=0;Branch=0;ALUOp[1]=0;ALUOp[0]=0;Jump=1;end6'b101011://swbeginALUsrc=1;RegWrite=0;MemRead=0;MemWrite=1;Branch=0;ALUOp[1]=0;ALUOp[0]=0;Jump=1;end6'b000100://beqbeginALUsrc=0;RegWrite=0;MemRead=0;MemWrite=0;Branch=1;ALUOp[1]=0;ALUOp[0]=1;Jump=1;end6'b000010://jbeginJump=0;endendcaseendEndmoduleDm.vmoduledm_4k(addr,din,we,re,clk,dout);input[11:2]addr;//addressbusinput[31:0]din;//32-bitinputdatainputwe;//memorywriteenableinputre;//memoryreadenableinputclk;//clockoutputreg[31:0]dout;//32-bitmemoryoutputreg[31:0]dm[1023:0];initialbegin$monitor(dm[102]=%d,dm[102]);endalways@(posedgeclk)beginif(we)begindm[addr[11:2]][31:0]=din[31:0];endif(re)begindout[31:0]=dm[addr[11:2]][31:0];endendEndmoduleExtend.vmoduleSigExtend(origin,ext_result);parametertem_WIDTH=16;input[tem_WIDTH-1:0]origin;output[31:0]ext_result;assignext_result={{(32-tem_WIDTH){origin[tem_WIDTH-1]}},origin};endmoduleIm.vmoduleim_4k(addr,dout);input[11:2]addr;//addressbusoutput[31:0]dout;//32-bitmemoryoutputreg[31:0]im[1023:0];initialbegin$readmemh(code,im);endassigndout=im[addr[11:2]][31:0];EndmoduleMips.v`includectrl.v`includeALUcontrol.v`includealu.v`includedm.v`includeim.v`includemux.v`includepc.v`includerf.v`includeextend.vmodulemips(clk,rst);inputclk;//clockinputrst;//resetwire[31:0]cur_pc;wire[31:0]pcAlu_result;wire[31:0]next_pc;wire[31:0]pc_plus4;wire[31:0]branch_mux_result;wire[31:0]instruction;wire[4:0]wreg;wire[31:0]rdata1;wire[31:0]rdata2;wire[31:0]extend;wirezero;wire[31:0]ALUresult;wire[31:0]rdata;wire[31:0]wdata;wire[31:0]aludata2;wire[3:0]alucontr;wireRegDst;wireJump;wireBranch;wireMemRead;wireMemtoReg;wire[1:0]alu_op;wireMemWrite;wireALUSrc;wireRegWrite;SigExtendext(.origin(instruction[15:0]),.ext_result(extend));assignpc_plus4=cur_pc+4;PCmyPc(.clk(clk),.rst(rst),.address(next_pc),.out(cur_pc));ALUpc_alu(.aluControl(4'b0010),.a(pc_plus4),.b({extend[29:0],2'b00}),.result(pcAlu_result));MUX32_2_1#(32)brunch_mux(.A(pc_plus4),.B(pcAlu_result),.sel(Branch&zero),.result(branch_mux_result));MUX32_2_1#(32)jump_mux(.A({pc_plus4[31:28],instruction[25:0],2'b00}),.B(branch_mux_result),.sel(Jump),.result(next_pc));im_4kmyIM(.addr(cur_pc[11:2]),.dout(instruction));controlUnitmyCunit(.instruction(instruction[31:26]),.zero(zero),.RegDst(RegDst),.Jump(Jump),.Branch(Branch),.MemRead(MemRead),.MemtoReg(MemtoReg),.ALUOp(alu_op),.MemWrite(MemWrite),.ALUsrc(ALUsrc),.RegWrite(RegWrite));RegFilemyRF(.clk(clk),.we3(RegWrite),.ra1(instruction[25:21]),.ra2(instruction[20:16]),.wa3(wreg),.data(wdata),.rd1(rdata1),.rd2(rdata2));MUX32_2_1#(5)writeReg_mux(.A(instruction[20:16]),.B(instruction[15:11]),.sel(RegDst),.result(wreg));dm_4kmyDM(.clk(clk),.addr(ALUresult),.din(rdata2),.we(MemWrite),.re(MemRead),.dout(rdata));MUX32_2_1#(32)regSrc(.A(ALUresult),.B(rdata),.sel(MemtoReg),.result(wdata));ALUcontrolmyALUcontr(.aluop(alu_op),.funct(instruction[5:0]),.aluControl(alucontr));MUX32_2_1#(32)alu_src(.A(rdata2),.B(extend),.sel(ALUsrc),.result(aludata2));ALUmyALU(.aluControl(alucontr),.a(rdata1),.b(aludata2),.result(ALUresult),.zero(zero));endmodule;Mux.vmoduleMUX32_2_1#(parameterWidth=32)(A,B,sel,result);input[Width-1:0]A,B;inputsel;output[Width-1:0]result;assignresult=(sel==1)?B:A;endmodulePc.vmodulePC(clk,rst,address,out);inputclk,rst;input[31:0]address;outputreg[31:0]out;always@(posedgeclk)beginif(rst)out=32'h00003000;elsebeginout=address;endendendmoduleRf.vmoduleRegFile(clk,we3,ra1,ra2,wa3,data,rd1,rd2);inputclk,we3;input[4:0]ra1,ra2,wa3;input[31:0]data;output[31:0]rd1,rd2;reg[31:0]rf[31:0];initialbeginrf[0]=0;endassignrd1=(ra1!=0)?rf[ra1]:0;assignrd2=(ra2!=0)?rf[ra2]:0;initialbegi