2选1数据选择器的VHDL描述

2选1数据选择器的VHDL描述ENTITYmux21aISPORT(a,b:INBIT;s:INBIT;y:OUTBIT);ENDENTITYmux21a;ARCHITECTUREoneOFmux21aISBEGINy=aWHENs='0'ELSEb;ENDARCHITECTUREone;译码器的设计architecturedec_behaveofe1issignalsel:std_logic_vector(0to3);beginsel(0)=en;sel(1)=a(0);sel(2)=a(1);sel(3)=a(2);withselselecty=00000001when1000,00000010when1001,00000100when1010,00001000when1011,00010000when1100,00100000when1101,01000000when1110,10000000when1111,00000000whenothers;enddec_behave;8-3优先编码器libraryIEEE;……;entityencoder83isport(ind:instd_logic_vector(7downto0);outd:outstd_logic_vector(2downto0));end;architecturebehaveofencoder83isbeginprocess(ind)beginifind(7)=‘1'thenoutd=111;elsifind(6)=‘1'thenoutd=110;elsifind(5)=‘1'thenoutd=101;elsifind(4)=‘1'thenoutd=100;elsifind(3)=‘1'thenoutd=011;elsifind(2)=‘1'thenoutd=010;elsifind(1)=‘1'thenoutd=001;elsifind(0)=‘1'thenoutd=000;elseoutd=000;endif;endprocess;endbehave;