数字预失真关键技术-Part3-V5

第三章数字预失真电路设计及实现第章数字预失真电路设计及实现第一节基于FPGA电路的预失真电路设计第节基于FPGA电路的预失真电路设计第二节预失真器参数的实时提取及实现第三节基于ASIC电路的数字预失真器设计及实现1.Intersil数字预失真线性化解决方案介绍数字预失真线性化解决方案介绍2.PMC-Sierra数字预失真线性化解决方案介绍3.TI数字预失真线性化解决方案介绍4Optichron数字预失真线性化解决方案介绍4.Optichron数字预失真线性化解决方案介绍第四节非线性建模及预失真性能快速评估软件介绍实施数字信号处理算法的DSP/FPGA平台自适应数字基带预失真功率放大器框图数字预失真器开发平台•DSPBoard:DSPBoard:–DualprocessorsTiger-SharcTS201:–Coreclock:500MHz–Internaldatamemory:•FPGA:STRATIXEP1S80Milkf250MH–Maximumclockfrequency:250MHz–2DACs:165MSPS–2ADCs:125MSPS–2ADCs:125MSPS•DSPalgorithmsexecutionissharedbetweentheFPGAforthehighspeedandrealtimepartandtheDSPforthecomplexandflibldflexibleprocedures.DSP/FPGADevelopmentPlatformforSoftwareEnabledTransceiversFPGA+DSPRFfrontendFPGADSPRFfront-endFPGA设计开发平台硬件：StratixIIDSP开发板@AlteraEP2S60F1020软件：QuartusIIVersion7.2&matlab开发工具开发工具•QuartusII–Robust,stabletoolforblock-baseddesign–IncludeseverythingyouneedtobuildSOPCdesignsItftllldi3rdtEDAtl–Interfacestoallleading3rdpartyEDAtools•SOPCBuilderCfibhittIPdfii–Configuresprocessors,busarchitectures,IPandfirmwareinonesimpleenvironment–InterfacestoNios,XAfamily&popularMicroprocessorfamilies,yppp•DSPBuilder–WorkswithMATLAB/SimulinktoprovideanFPGAdevelopmentppenvironmentthatisidealforsystemsengineers–WorkswithSOPCBuildertogiveaC-basedDSPdesignflow6用DSPbuilder设计FIR滤波器用DSPbuilder设计FIR滤波器7基于FIR的记忆多项式预失真器设计a1,0FIR0x(n)Z-1××∑1,0a1,1()Z-1×a1,2x(n)|x(n)|FIR1∑z(n)x(n)|x(n)|FIR1x(n)|x(n)|11FIR11基于FIR的记忆多项式预失真器由无记忆多项式子系统、FIR滤波器群和加法组成群和加法器组成。基于FIR的记忆多项式预失真器实现基于的忆多项式预失真器实现采用递归思想降低模值计算的迭代次数，串并转换无记忆多项式子系统设计IQ两支路输入，实现串并转换功能，14bit输入，14bit输出CORDIC算法•Hardwareefficientalgorithmforcomputingfunctionssuchas:–TrigonometricHyperbolic–Hyperbolic–Logarithmic•Iterativesolutionthatusesonlyshiftsandadding/subtractinggg–Highperformanceasnomultiplicationsanddivisionsdivisions–Simple/lesshardwarerequired11第三章数字预失真电路设计及实现第章数字预失真电路设计及实现第一节基于FPGA电路的预失真电路设计第节基于FPGA电路的预失真电路设计第二节预失真器参数的实时提取及实现第三节基于ASIC电路的数字预失真器设计及实现1.Intersil数字预失真线性化解决方案介绍数字预失真线性化解决方案介绍2.PMC-Sierra数字预失真线性化解决方案介绍3.TI数字预失真线性化解决方案介绍4Optichron数字预失真线性化解决方案介绍4.Optichron数字预失真线性化解决方案介绍第四节非线性建模及预失真性能快速评估软件介绍12自适应算法实现预失真器参数的提取S2.1)HardCoreAdvantages•HighPerformance922TDMIoneMIPS200g•Time-to-Market•LotsofOn-ChipMemory•LeverageLargeExistingCodee(Dhryst100SoftCoreAdvantages•Flexibility•LowCostBaserformance2050•PortableDesign•Scalability•ObsolescenceProof•FitsBroadRangeofAlteraPLDFamiliesPer200SoftCoreHardCore•FitsBroadRangeofAlteraPLDFamiliesSoftCoreHardCore13传统脉动阵列)(),1(),...,1(),(MxMxnxnx−−)1(),2(),...,1(),(−−−MxMxnxnx局限局限11无法处理非线性模型)1(),2(),...,1(),(xxnxnx−)()1()1()(MyMynyny+局限局限11无法处理非线性模型0121,,...,,−−)(),1(),...,1(),(MyMynyny+−局限局限22线性阵列的吞吐量有限实时性差，实时性差新脉动阵列---三角部分R00R01R11x(2)x(2)/x(2)///P*M-1x(M)x(M-1)x(N)00000N-M+1预加阵列原三角阵列9注意此处是R33R22R02R03R12R13R23x(2)/x(2)/2x(1)x(1)x(2)x(N-M+1)00000//P-1P=3,M=2的特例R55R44R04R05R14R15R24R25R34R35R45x(1)/x(1)/x(1)/x(1)/2(2)(M)(M+1)(N)00000////P-1U0U1U2U3U4U5y(2)y(M)y(M+1)y(N)00000innx,)(innx)(innx)(0)(0)(:,=innx初始化outcinR1:=c初始化RinsRcR****2/1+=λRinsRcRinout***2/1λ−=outnx)(ininoutnxnxnx)(*)()(,=innx)(innx)(:初始化0)(=innxoutsoutRinR00==Rs1:初始化RinsRcR***+=λccout=ssout=22*inRxtemp+=λtempRiinoutMnxnx)()(1=−outMnx)(1−in)(in)(0)(=innx1,..1,0−=Mi001===RscinintempRsin/=tempRc/*2/1λ=tempR=新阵列的三角阵列和功能函数15新脉动阵列-逆向阵列部分W2RUinWout1Wout20210===WoutWoutUin时，RUinWoutWout/21==Wout000UtWiUi时UinWoutUoutWinR000===UoutWinUin时，WinRUinUout*−=WinWout=新阵列的逆向阵列结构图和功能函数16新脉动阵列的记忆项式模型实现UwRwRwRwRwRwR=++++++******三角阵列QR分解所实现的结果nnnnnnUwRwRwRwRUwRwRwRwRwRUwRwRwRwRwRwR=++++=+++++=++++++*...****...****...224243232221141431321211100404303202101000nnnnUwRwRUwRwRwR=++=+++*...**...**4444433434333nnnnUwR=*#逆向阵列实时处理权值的依据11=−−RUwMM0,...3,2)(111,11−−=−=∑+=−−MMkwRURwRnkjjkjkkkkMMM17IAlteraNiosIIDPD参数提取解决方案AlteraNiosIIDPD参数提取解决方案TDUCTDUC--IQToDUCToDUCQTableIQQLUT(I&Q)~100entries12bitWordlengthabeAddressCalc(I2+Q2)1/212bitWordlengthSAdaptiveEst.AlteraMegaCoreIPDelayMatchingCompare&EstimateRSI&QDemodulatorFFTLoopDelayEstimatorEmbeddedProcessor18主要实现部分主要实现部分实实•Forwardpath:I,Qmultipliers•Lookuptable:DualportmemoryLookuptable:Dualportmemory•Feedbackpath–Nioswithcustominstructions–CORDICacceleration–Multiplyacceleration19定制指令实例定制指令实例OptionalFIFO,Memory,OtherLogicALUALU+定实定实NiosProcessorIntegerMult/ExampleALUOnly+IntgrMultALU+CmplxMultIntegerMult/ComplexMultMultLoopTime(us)11.1900.5600.011LoopClocks1119561.1MULClocks2533-x50ComplexMultsperSecond89K1.8M90.9MHardwarex50LoopTime=ExecutionofasinglecomplexmultiplyLoopClocks=NumberofclockstoexecutesingleiterationMULClocks=NumberofclockstoexecutetheMULonlyAccelerator20数据流数据流I/PtoDPDI/PtoDPDFFAddressDDCDDCI1Q1..DPDDPDFromPAFromPAUpdateLUTUpdateLUTAddressCalculationDDCDDCSn+1=Sn-α*escaleSn+1=Sn-α*escaleInQn..LUTLUTFFTFFTSn+1SnαescaleRn+1=Rn-α*erotateSn+1SnαescaleRn+1=Rn-α*erotateI1Q1InQn....LoopDelayLoopDelayClCl()()α=tan-1(.)DelayMeasDelayMeasCmplxMultCmplxMultDelayMatchingDelayMatching(.)__Gain(.)__GainVerrorVerrorH/WAcceleratorH/WAcceleratorProgrammableLogicImplementationProgrammableLogicImplementationSoftwareImplementation(Nios)SoftwareImplementation(Nios)Implem