视频信号高速处理硬件平台系统的设计与实现

华中科技大学硕士学位论文视频信号高速处理硬件平台系统的设计与实现姓名：李景奇申请学位级别：硕士专业：模式识别与智能系统指导教师：田金文20050401V2090ISOITUJBIGJPEG64KH.2611.5MMPEG-1MPEG-2H.2632090,,,,,,,,,,IT,TIDSPTMS320C6414,DSP,FPGA,CPLDDSPA/D,CPLD,,DSP,FPGA,USB.,FPGA,DSP,,IICA/DFPGA,,,AD/DADSPFPGAUSBVIAbstractTheresearchofDigitalvedioandimagehavegonethrouthhalfacentury,havegotlotsofprogressintheoryandengineering.wheninthe20century90’years,atthecooperationofinternationalorganization,ISOandITUcollectthoseprogressandmakeseveraluniversalVideoandimageprocessstandard,includetheJBIGwhichisusedintwo-valueimage,JEPGwhichisusedincontinuegrayvalueandcolorstilliamge,H.261whichisusedin64Kvideotransmission,MPEG-1whichisusedin1.5Mvideoandaudiotransmissionandstorage,MPEG-2whichisusedhighqualitydigitalvideoandaudiotransmissionandstorage,H.263whichisusedinlowratevideoencoding.thesestandardarithmeticareconstituteof4kindsoftechnology:thecompensationofmovement,orthogonaltransformationthesetechnologystandfortheresearchleveloftheearly90’sinthe20cuntury.Asthevideobroadcast’stotaldigitalization,traditionalvideomasswillintrojectwithothermethodininformationandtelecommunicationintechnologyandfunction,thusformafullnew.hugedigitalvedioindustry,thenewbornedindustryhavearousedtheabroadattention,thedevelopedcountryhaveseparatelymappedouttheanologvideotodigitalvideoplanandindustrytargetaccordingtodifferentsituation.Thedigitalvideohasbeenseenasanothernewstrategytechnologyafterthetelecommunication.Theresearchandprocessofvideosignalistheemphasesofpresentsignalprocess,thispaperintroduceavideorealtimeimageprocessorsystem’sdesignandconstructionwhichbasedonTI’highperformanceDSPTMS320C6414,analyzeseveralkeyproblemsonhighSpeedelectrocircuitDesign,Inthisvideoandimageprocesssystem,,FPGAisusedasamainlogicunit,andDSPcontroltorealizethedataacquisitionforvideosignal,andthethedspisthecoreprocessor,usetheCPLDascontrollogictorealizeserevalvideoformatsignaldatacollection.ThedesignofthissystemincludeA/Dconvertcircuitmodule,videosignalFormatreceivecontrolCPLDmodule,videodatastoragemodule,videosignalcoreprocessdspModule,FPGAdatatransmittingmodule,USBhighspeedinterfacemoduleandpowersupplyModule.onthebasisofintroducesystemconstitueprinciple,expatiateindetailtheconstitueloftheDatacollectionandthecontrollogicoftheFPGA,DSPrespondtheinterruptionandVIItransferthedataandstorethedata.checkandchangethepattern,thevideoA/Dconvertmodule’sinitializationbasedontheIICprotocol.UsingFPGAtorealizevideosignalcollectionandprocessionwillenchancethesystemcapability,andeasytodesignanddebug.Italsohassuchadvantagesasadaptabilityandflexibility.summarizethesystemprincipleandtheimplementmethod.Keywords:videosignal;AD/DA;HighSpeedelectrocircuitDesign;DSP;FPGA;USB11.1.1.1.1.1.[1-2]1.1.2.à1SIFNTSC4:4:4352X240X3=253KB253X30=7.603MB/sCD-ROM650/7.603/60=1.422CCRPAL4:4:4720X576X3=1.24MB1.24X25=31.3MB/sCD-ROM650/31.3/60=20.9Landsat-32340X3240X7X4=212MB212MBX30/=6.36Gbà1[3]2Huffman2343)1::2:/:PSNR31.2.1.2.1.1.2.1.1.~1.2.1.2.2090ISOITUJBIGJPEG64KH.2611.5MMPEG-1MPEG-2H.26320902090ISOITUJBIGJPEG64KH.2611.5MMPEG-1MPEG-2H.2632090ISOITU4ISO:JBIG10:1JPEGMPEG-1MPEG-21.5Mbps2-15MbpsITU:H.261H.26364Kbps1.3.2090Internet[4-7]MPEG-4FineGranularScalable,FGSProgressiveFine5GranularScalable,PFGSFGS1dBJPEG2000JPEG2000JPEGFGSMPEG-423dB2090Internet(1)JPEG2000(ROI)MJPEGMPEG-4,H.264+MPEG-4AVC=JVT,AVS(2)1.4.6,.DSP72.2.1.2.1.1.1)23)(1)(2)BMPTIFGIFD3DS3DDXFCADWMF2.1.2.8YUV4:2:2YUV4:1:1YUV4:2:02-12.1.3.1PAL:625/,25/,50/NTSC:525/,30/,60/21PAL:864/,13.5Mhz432/,6.75Mhz2NTSC:9:858/,13.5Mhz429/,6.75Mhz3::810PCMo02551154o16=black,235=whiteo128=nochrominance2-14216Mbps(D1-DTR8),270Mbps(D5-DTR10).1YUV4:2:2216Mbps/625*864*8*25=108Mbps625*432*8*2*25=108Mbps2YUV4:1:1162Mbps625*864*8*25=108Mbps625*216*8*2*25=54Mbps3YUV4:2:0162Mbps625*864*8*25=108Mbps625*432*8*25=54Mbps102.2.2.2.1.CCIR-6011)CCIRNTSCPALSECAMfs13.5MHzPALSECAM864NTSC8584:2:2fsfs26.75MHz3.375MHz2)PALSECAM864NTSC858CCIR601720PALSECAM576NTSC484CCIR720×484HDTVHighDefinitionTV2-1NTSC720×48030PALSECAM720×576253)CCIR-6014:2:2CbYCrYCbYCrY……11SAVEAV720aITU-6012-2ITU-6012-2ITU-601VD[15..0]TTLYUVVSYNCTTLHSYNCTTLDVALIDTTLFIELDTTL0PCLKTTLGNDbITU-6012-1aVSYNCHSYNCDVALIDPCLKbtcc30ns,74ns(13.5Mhz)cPCLKts14ns,tcc/4(18.5ns)dPCLKth11ns,tcc/2(37ns)c)ITU-601VSYNCHSYNCFiledDVALID12aDVALIDbFiledcVSYNCdHSYNC2-22-3SAVEAVF=0forfirstfield1forsecondfield;V=0or1(inVBI-verticalblankinginterval)H=0inSAV,1inEAV;P0,P1,P2,P3132-4VBIVF2-5XY.0d.2-3CCIRRec.60114CCIR6018256220225fs42213.5(MHz)×8(bit)2×6.75(MHz)×8(bit)=27Mbyte/s44440271027068025272.2.2.CCIR-656CCIR-656SAVEAV,CbYCrYCb27M/720EAVSAV720YCbCr360144001439525/60276625/50288525/601716625/501728SAVEAV433FF/000/0004XYZ“XYZ”8F7V6H“SAV”“EAV”6152-1CCIR-6561VPO5V242216CCIR601.3CCIR656.1I2C-busbitTCLO=0,VPO15toVPO8=VPO7toVPO0=CCIR6562I2C-busbitTCLO=1,VPO15toVPO8=CCIR656,VPO7toVPO0=3-state4HREF=LOWRGBlevelsaresetto16(10hex).RGB16-bitisachievedbydroppingtheLSBsofthe8-bitsignals(afterditheringifdesired).5CREF=0(seeFig.3-1).6CREF=1(seeFig.3-1).162-2SAVEAVF=0forfirstfield1forsecondfield;V=0or1(inVBI-verticalblankinginterval)H=0