FPGA直流电机闭环控制

`timescale1us/1nsmoduletb;//Inputsregclk;regrstn;regkey_en;regdir_en;regspeed_rt;regCHA;regCHB;//Outputswirepwm_N1;wirepwm_N2;wirepwm_N3;wirepwm_N4;//InstantiatetheUnitUnderTest(UUT)ZLDJ_TOPuut(.clk(clk),.rstn(rstn),.key_en(key_en),.dir_en(dir_en),.CHA(CHA),.CHB(CHB),.pwm_N1(pwm_N1),.pwm_N2(pwm_N2),.pwm_N3(pwm_N3),.pwm_N4(pwm_N4));initialbegin//InitializeInputsclk=0;rstn=0;key_en=0;dir_en=0;CHA=0;CHB=0;#1000;rstn=1;#500;key_en=1;#500;CHB=1;#10000;CHB=0;#10000000;$finish;//Wait100nsforglobalresettofinish//Addstimulushereendalways#10clk=~clk;endmodulemoduleZLDJ_TOP(clk,rstn,key_en,dir_en,CHA,CHB,pwm_N1,pwm_N2,pwm_N3,pwm_N4);inputclk;inputrstn;inputkey_en;inputdir_en;inputCHA;inputCHB;outputpwm_N1;outputpwm_N2;outputpwm_N3;outputpwm_N4;wire[15:0]speed_set;wirepwm_out;//instancemoduleZLDJ_DIRu_zldj_dir(.clk(clk),.key_en(key_en),.rstn(rstn),.dir_en(dir_en),.pwm_out(pwm_out),.pwm_N1(pwm_N1),.pwm_N2(pwm_N2),.pwm_N3(pwm_N3),.pwm_N4(pwm_N4));//speed_meawireCLR;wireENA;wireLOAD;SPEED_MEAu_speed_mea(.clk(clk),.rstn(rstn),.CLR(CLR),.ENA(ENA),.LOAD(LOAD),.clk_pid(clk_pid));wire[15:0]speed_act;//speed_trSPEED_TRu_speed_tr(.clk(clk),.rstn(rstn),.CLR(CLR),.ENA(ENA),.LOAD(LOAD),.CHA(CHA),.CHB(CHB),.speed_act(speed_act));//pidPIDu_pid(.clk(clk_pid),.speed_act(speed_act),.speed_set(speed_set));//pwm_outPWM_OUTu_pwm_out(.clk(clk),.rstn(rstn),.speed_set(speed_set),.pwm_out(pwm_out));endmodulemoduleZLDJ_DIR(clk,key_en,rstn,dir_en,pwm_out,pwm_N1,pwm_N2,pwm_N3,pwm_N4);inputclk;inputkey_en;inputrstn;inputpwm_out;inputdir_en;outputpwm_N1;outputpwm_N2;outputpwm_N3;outputpwm_N4;regpwm_N1;regpwm_N2;regpwm_N3;regpwm_N4;always@(posedgeclkornegedgerstn)beginif(!rstn)beginpwm_N1=#10;pwm_N2=#10;pwm_N3=#10;pwm_N4=#10;endelseif(!key_en)beginpwm_N1=#10;pwm_N2=#10;pwm_N3=#10;pwm_N4=#10;endelseif(dir_en)beginpwm_N1=#1pwm_out;pwm_N2=#10;pwm_N3=#10;pwm_N4=#1pwm_out;endelsebeginpwm_N1=#10;pwm_N2=#1pwm_out;pwm_N3=#1pwm_out;pwm_N4=#10;endendendmodulemoduleSPEED_MEA(clk,CLR,ENA,LOAD,rstn,clk_pid);inputclk;//50kHZinputrstn;outputCLR;//rstcounteroutputENA;//counter'senableoutputLOAD;//loaddataoutputclk_pid;regclk_pid;regCLR;regENA;regLOAD;reg[15:0]cnt;always@(posedgeclkornegedgerstn)beginif(!rstn)beginCLR=#10;ENA=#11;LOAD=#10;cnt=#10;clk_pid=#10;endelseif(cnt==3000)beginENA=#10;LOAD=#11;cnt=#1cnt+1;endelseif(cnt==3500)beginCLR=#11;LOAD=#10;cnt=#1cnt+1;endelseif(cnt==4000)beginCLR=#10;ENA=#11;cnt=#10;endelsecnt=#1cnt+1;end//always@(posedgeclkornegedgerstn)always@(posedgeclk)beginclk_pid=#1LOAD;endendmodule//speed_meamoduleSPEED_TR(clk,rstn,CLR,ENA,LOAD,CHA,CHB,speed_act);inputclk;inputrstn;inputCLR;inputENA;inputLOAD;inputCHA;inputCHB;//outputclk_pid;//regclk_pid;output[15:0]speed_act;reg[15:0]speed_cnt;//assignspeed_act=(LOAD)?(speed_cnt*10):0;assignspeed_act=(LOAD)?(5*speed_cnt):0;wireCLR;wireENA;wireLOAD;always@(posedgeclkornegedgerstn)beginif(!rstn)speed_cnt=#10;elseif(CLR)speed_cnt=#10;elsespeed_cnt=#1speed_cnt;end//always@(posedgeclkornegedgerstn)always@(posedgeCHB)beginif(ENA)speed_cnt=#1speed_cnt+1;elsespeed_cnt=#1speed_cnt;endendmodulemodulePID(clk,speed_act,speed_set);inputclk;input[15:0]speed_act;output[15:0]speed_set;parameterspeed_exp=2800;parameterKi=1;parameterKp=1;//inoutsignalreg[15:0]en;reg[15:0]en_1;wire[15:0]en_cha;wire[15:0]Ki_en;wire[15:0]he;wire[15:0]uk;assignspeed_set=speed_act+uk;//geten,en=speed_exp-speed_act,//subh1(.a(speed_exp),.b(speed_act),.s(en),.clk(clk));always@(posedgeclk)beginen=#1speed_exp-speed_act;en_1=#1en;end//geten_cha,en_cha=en-en_1subh2(.a(en),.b(en_1),.s(en_cha),.clk(clk));//getKi_en,ki_en=T/Ti*enmultiplyh3(.clk(clk),.a(Ki),.b(en),.p(ki_en));//gethe,he=en_cha+Ki_enaddh4(.a(en_cha),.b(Ki_en),.s(he),.clk(clk));//getdel,del=Kp*hemultiplyh5(.clk(clk),.a(Kp),.b(he),.p(uk));endmodulemodulePWM_OUT(clk,rstn,speed_set,pwm_out);inputclk;inputrstn;input[15:0]speed_set;outputpwm_out;reg[15:0]cnt1,cnt;regclk1;assignpwm_out=clk1;always@(posedgeclkornegedgerstn)beginif(!rstn)beginclk1=1;cnt1=0;cnt=0;endelseif(cnt==speed_set&clk1==1)beginclk1=~clk1;cnt=cnt+1;endelseif(cnt1==2000)beginclk1=~clk1;cnt1=0;cnt=0;endelsebegincnt1=cnt1+1;cnt=cnt+1;endendendmodule