基于FPGA的PCI总线接口控制器的设计

南京航空航天大学硕士学位论文基于FPGA的PCI总线接口控制器的设计姓名：王丽媛申请学位级别：硕士专业：电路与系统指导教师：臧春华20080201iIntel1991PCI(PeripheralComponentInterconnect)PCIPCIPCITOP-DOWNPCIFPGASDRAMPCIPCIFPGAPCIPCBPCIDDK(VHDL)PCITOP-DOWNVHDLPCBSDRAMFPGAPCIiiAbstractThePeripheralComponentInterconnect(PCI)busisahigh-bandwidth,plug-and-playbusprotocoldesignedtomeettheperformancedemandsoftheperipheralsoftoday'shigh-performancePCsandworkstationsandtheirlargebandwidthapplication.Itisrapidlybecomingwidelyacceptedinthecomputerindustryasitopensdoorstoperformancedemandingapplicationsuchasvideoandaudiosystem,graphicsacceleratorboards,3Dnativesignalprocessing,networkadapter,anddatastoragedevices.ThisdissertationresearchesthedesignandimplementationofPCIbusinterfacecontroller,basedonTop-Downdesignmethod.ThePCILocalBusSpecificationisalsoanalyzedcomprehensively.ThewholeworkisdescribedwithVerilogandimplementedbyFPGA.ThisdissertationiscluedbythedesignandimplementationofPCIbusinterfacecontroller,anditexpatiatesonthePCIbusinterfacecontroller,whichinvolvesallprocessesofdesign,coding,simulation,synthesisandtest.Inthisresearch,thedesignofPCIbusinterfacecontrollerismainlydiscussed.ItspremiseisPCIBusSpecificationanditsstickingpointsaretoanalysisthefunctionandarchitectureofPCIbuscontroller.Thewhole-designandallsubmodulesimplementationofPCIbuscontrollerarealsodiscussedindetailinthispaper.ThisdissertationfinishesthedesignofPCIbusinterfacecontroller,andithasalsocompletedthefunctionsimulationaswellastimingsimulationafterplacingandrouting.APCBboardisdesignedtotestthiscontrollerandtheresultoftestprovesthevalidityofthiscontrollertocontinuedresearches.Keywords:PCILocalBus,TOP-DOWN,FPGA,VHDL,PCB,SDRAMControllerv2.1PCI……………………………………………………………..92.2PCI…………………………………………………………102.3PCI………………………………………………………142.4……………………………………………..192.5……………………………………………..192.6……………………………………………………..202.7……………………………………………………..213.1PCI……………………….273.2Memory……………………………………….293.3I/O……………………………………………..293.4……………………………………………………..323.5……………………………………………………..333.6PCI……………………………………………………333.7SDRAM………………………………………………363.8SDRAM……………………………………………364.1PQFPPCI………………………………..424.2Memory..……………………………………444.3Memory……………………………………..444.4Memory………………………………………..454.5Memory………………………………………..454.6FPGA…………………………………………………….….484.7JTAGAS………………………………………48,()11.190WindowsNTCPUISAEISAPCIPeripheralComponentInterconnection1991InterPCICPUPCI[4]CPUCPUPCIPCI33MHZ32PCI132MB/S64PCI264MB/SPCPCIPCIPCIPCIPCI2.2PCIPCIPCIPCIPCI33MHZ32FPGAPCI2016PCII/OPCICPU[30][33]1.21.2.1CPUI/OCPUCPUI/O[1][9]CPUCPUCPU1.CPU2.CPU3.I/OI/O31.2.2PCII/OMCAVESAISAPCIPCIBM1981PC/XT8bit8088PCPC/XT1984IBM16-bitIntel80286PC/AT16bitPC/ATIBMPCIBMPCISAIndustryStandardArchitecture[33]ISA8/16bit8MB/sCPU80CPUPC‘98ISAInteli810ISA286386SXCPU8/16bitISA32-bit386DX19889ISA32-bitEISAExtendedISAISAEISA8MHz8/16bitISA32-bit32MB/s.EISA2090PCICPUISA/EISACPU1992Intel48632-bitPCIPCI33MHz133MB/s33MHzX32bit/8ISA199364-bitPCIPCI66MHz.32-bit33MHzPCI[39]FPGAPCI4PCICPUCPUCPU1.3EDA:FPGACPLDVHDLPCI1.3.1EDAEDA(HDL)EDA:1.EDA2.EDA3.EDA4.EDA.5.EDAF5[45]EDAEDA1.3.2Top-Down(Bottom-Up)(Top-Down)Top-Down:1.HDLRTLHDL2.3.4.VHDL5.VHDLVHDLFPGAPCI66.Top-Down1.3.3VHDLVHDL(VeryhighspeedHardwareDescriptionLanguage)80198712IEEE-STD-1076VHDL:1.VHDLTop-Down,Botom-Up,(Library-Based)FPGA2.VHDLRTLVHDLHDLVerilogICPCB3.VHDLHDLVHDL4.VHDLVHDLIEEEVHDLAdaVHDL[6][63]1.3.4FPGACPLDPLDPLDFPGACPLD7FPGACPLD(FPGA:FieldProgrammableGateArray)(CPLD:ComplexProgrammableLogicDevice)EDAEDAPALGALFPGACPLDICFPGACPLD[14]:1.FPGACPLD2.3.FPGACPLDPROMPROM4.FPGACPLDFPGACPLDICEDAFPGACPLD1.4PCIPCIPCIEDAFPGAPCBPCIPCIPCIPCIFPGAPCI8PCISDRAMPCIPCIPCB9PCI2.1PCIPCIPerpheralComponentInterconnection,Inter19925V2.22.1[33]2.1PCI2.1PCIPCIPCIPCIPCI/Cache/PCIPCII/OPCIPCIFPGAPCI10PCIPCIPCIPCI[42]2.2PCI2.2PCIPCI3.3V5V3.3VPCI5V3.3V5V3.3V5V3.3V[5]2.2PCIPCIPCI112.3PCI2.3.1PCI(peripheralcomponentinterconnect)ISAEISAIBMMCA:1.Wbit2.3.:Q=W*f/NQ(MB/s),Wf,N4.;5.6.2.3.2PCIPCI[9]1.PCIPCI33MHZ32132MB/SISA5MB/S322.PCI1PCI3.PCIFPGAPCI12PCI4.PCIPCIPCI5.PCI6.PCI3.3VPCIPCIPCIPCIPCII/O7.PCIISAEISAMCAPCIISAEISAMCA8.PCI64/64PCI64264MB/SPCI3264133264PCI9.PCIPCI/PCI5010.PCIPCIPCIEISA2.4PCIPCI47492.3[2]InOutt/s/s/t/sod:FPGAPCI1423PCI##2.3PCI1.CLKinPCI33MHZ0HZDCPCIPCIRST#INTA#INTB#INTC#INTD#CLKRST#inPCIPCIPCIPCISERR#REQ#GNT#ADC/BE#PAR2.15AD[310]t/s/FRAME#IRDY#TRDY#PCIPCIAD[310]32I/OAD[70]AD[3124]IRDY#TRDY#C/BE[30]#t/sAD[310]3.FRAME#s/t/s:FRAME#FRAME#IRDYs/t/s:TRDYAD[31:0]TRDY#s/t/s:IRDYAD[31:0]IRDY#TRDY#STOP#s/t/s:LOCK#s/t/s:IDSELin:DEVSEL#s/t/s:4.REQ#t/s:FPGAPCI16REQ#GNT#t/s:GNT#5.PCIPERR#s/t/s:DEVESEL#PERR#PERR#PERR#SERR#od:6.PCIINT#PCI4INTA2.5PCIPCII/OPCI[2]1.AD[1:0]AD[1:0]00AD[1:0]10CacheAD[1:0]x13217AD[31:2]DWORD2.I/OI/OI/OAD[31:0]32AD[1:0]C/BE[3:0]#C/BE[0]#AD[1:0]00C/BE[3]#AD[1:0]11C/BE[3:0]AD[1:0]3.25664AD[1:0]011PCIAD[1:0]000PCI0AD[7:2]64AD[10:8]2.6PCIPCIRST#INTA#INTB#INTC#INTD#CLKPCI[2]1.FRAME#FRAME#FRAME#2.IRDY#3.TRDY#FRAME#IRDY#FRAME#IRDY#TRDY#IRDY#TRDY#FPGAPCI18XRDY#IRDY#TRDY#XRDY#IRDY#TRDY#FRAME#IRDY#TRDY#FRAME#IRDY#PCI1.FRAME#IRDY#/2.IRDY#FRAME#FRAME#3.IRDY#IRDY#FRAME#TRDY#STOP#DEVSEL#TRDY#ST