高频交易超低延迟交换器usecasesNICFPGA

1CaseStudies高頻交易專用Switch使用案例MarketDataDistributionExchangeTradingSystemsExaLINKFUSIONCASESTUDY12•ExchangetoServer(sub-5ns)MarketData1對n同時發佈所有Latency5ns多台分析系統可同時收到MarketDataMuxing/AggregationExchangeTradingSystemsExaLINKFUSIONCASESTUDY23ExchangetoServer(s)(sub-5ns)Server(s)toExchange(55ns)Mux/Aggrgate各交易需求至交易所只要46ns46nsElectronicPatchPanel/MediaConverterPrimaryserverExchangeBackupserverSwitch/RouterExaLINKFUSIONCASESTUDY3•Commonuse-casewhichreducesneedforremotehandsatdatacentresandsimplifiesconfigurationmanagement•AllconnectionsintherackmadeviatheExaLINKFUSION(SFP+Transceiver)•Sub5nslatency=invisibletothenetwork•Media/Speedconversion10G/1G4與其它異質Switch/Router界接NetworkmonitoringPrimaryserverExchangeBackupserverSwitchMonitoringserverExaLINKFUSIONCASESTUDY4•Flexiblysampleandmonitorarangeofports•Tapping&Mirroring5網路流量Tapping後加上精準TimeStamp,可作為網路效能分析來源KillSwitch/CircuitBreakerPrimaryserverExchangeBackupserverSwitchRiskMonitoringserverExaLINKFUSIONCASESTUDY5•Useas“killswitch”usingJSONAPI6XXXXXXXXXXXXX可程式化Trigger即時中止所有動作•ExaLINKFUSIONusedasmaster•NormalExaNIC/IndustrystandardcardsoperatingasPTPslaves(usinghardwaretimestamping)•BoundaryclockmodeonExaLINKFUSION(future)GPSantennaTimeSynchronization-PTPExaLINKFUSIONCASESTUDY6精準校時•PPSoutfromExaLINKFUSIONcascadedthroughrack•Tightsynchronizationachievable(betterthanPTP)•OptiontotransmittimecodeoverPPSporttosynchronizeactualtimeofday–comingsoonTimesynchronization-PPSGPSantennaExaLINKFUSIONCASESTUDY7精準時間同步•UsingX86InternalModuleforExaLINKFUSION•IntegratedX40(8x10GInterfaceswithvirtualconnectivitybetweenFusionportsandembeddedX40ports)•X40canseein/outPPSFusionportfortiming•Upto3TBoflocalstoragewithlineraterecordingat10G•Patch,Tap,Mirror,Mux,Switchtraffictointernal/externalrecordserver•PrecisionTimeStampingto2.8nsCapture&Record(Internal&External)GPSantennaExaLINKFUSIONCASESTUDY8精準擷取網路封包至外部系統,TimeStamp可小至2.8ns•UsingX86InternalModuleforExaLINKFUSION•ShipswithCentOS7OperatingSystembutnotlimitedto•TradingLogic/InlineRiskChecks•VirtualconnectivitybetweenFusionportsandembeddedX40ports•FPGADevKitAvailableforonboardX40•IntelActiveManagementTechnologySupportEmbeddedTradingLogic/RiskServerGPSantennaExaLINKFUSIONCASESTUDY9ExchangeTradingSystems選配內建x86/FPGA模組-可自行開發系統與Switch更緊密結合Layer-2Switching(Untagged/802.1Q)L3SwitchTradingSystemsExaLINKFUSIONCASESTUDY1011VLANTrunkVLAN100VLAN200ExchangeExchangeGPSantenna可依需要支援L1:TappingL1.5:Mux/AggregationL2:SwitchingAPOWERFULCOMBINATION…FPGAModule:XilinxKintexUltrascaleKU115288MbitQDR4SRAM2xDDR4DIMMOCXO,TPMx86Module:IntelCore-i7Skylake,4cores@2.8GHz32GBDDR4-2133MT/sDualmSATASSDsM.2PCIeNVMeSSDOnboardlowlatencyExaNICX40NICs•World’sLowest-Latency•10GbE,1GbE,100M•Transparentkernelbypass-Exasock•API-libexanic•Bridging&Mirroring•FlowSteeringwith32userspace2MBbuffers–128IPrulesperport,64MACrulesperport•Hardwaretimestamping–Allreceivedframes,mostrecentTXframe–Timesynchviahost,hardwareassistedviaPTP,optionalPPS•FDK-beingusedfor:–mktdatafiltering/tagging.linearbitration–simplecard-basedtradingstrategiesExaNIC-GrandMaster16PTPPPSGPSExaNICX10-HPT17MeasuredTargetTimestamping0.25nsUtility:exanic-benchmarkerExaNICV5PHighDensityFPGAprogramFPGA程式開發20FPGA開發流程21FPGAboards:OnExaNICNetworkAdaptorOnModuleinsideExaLINKFUSIONSwitchXilinxDesignSoftware:VivadoDesignSuite(7-Seriesandnewer)SystemEdition(inthelab)WebPACKEdition(free)FPGA設計與實踐HighLevelLanguageC,C++,SystemCHardwareDescriptionLanguageVHDLorVerilogVivadoHLSVivadoHLS23ExaNICTradingonFPGA24Interfaces:AllEthernetPorts,DMAengines,userregisterspaceandusermemoryspace.SupportedDevices:ExaNICX10featuringXilinxKintexUltrascaleXCKU035ExaNICX40featuringXilinxKintexUltrascaleXCKU035Buildprocess:Makefileandbuildscriptsincluded.SimulationandVerification:Fullbusfunctionalmodelallowssimulationofallinterfaces.FPGADevelopmentKitExaNIC25FDKInterfacesExaNIC26ExaLINKBlockDiagramoftheFusionFPGAModule27ExaLINKConnectivityoftheFusionFPGAModule28ExaLINKVivadoconnectingtotheFusionDebuggingwithVivado29ExaLINKVivadoHWManager&SysMonDashboard