北交模拟试卷

BeijingJiaotongUniversityFinalExaminationCourse:ComputerArchitectureLecturer:AiLihua，WangBing（NOTE：4partsin2hours:total100points）PartNo.Part1Part2Part3Part4Part5TotalScoreExaminerPleaseshowyourworkCLEARLYforallproblems.Ihopeyouenjoythetest!Part1—Markonlyoneanswerforeachquestion[10points]1.Asuperscalarprocessorhas()(a)multiplefunctionalunits(b)ahighclockspeed(c)alargeamountofRAM(d)manyI/Oports2.On-chipcachehas()(a)loweraccesstimethanRAM(b)largercapacitythanoffchipcache(c)itsowndatabus(d)becomeobsolete3.()datahazardsarenotpossibleintheDLXin-orderinstructionissueandin-orderexecutionmulticyclepipeline?(a)WAR(b)WAW(c)RAW(d)RAR4.PipeliningimprovesCPUperformancedueto()(a)reducedmemoryaccesstime(b)increasedclockspeed(c)theintroductionofparallellism(d)additionalfunctionalunits5.Cachememoryenhances()(a)memorycapacity(b)memoryaccesstime(c)secondarystoragecapacity(d)secondarystorageaccesstime6.RISCmachinestypically()(a)havehighcapacityon-chipcachememories(b)havefewerregistersthanCISCmachines(c)arelessreliablethanCISCmachines(d)execute1instructionperclockcycle.7.WhichofthefollowingisNOTacomputerperformancemetric:()(a)MIPS(b)FLOPS(c)SPECbenchmark,(d)RISC8.Givena5stagepipelinewithstagestaking1,2,3,1,1unitsoftime,theclockperiodofthepipelineis:()(a)8(b)1/8(c)1/3(d)39.Theaveragememoryaccesstimeforamachinewithacachehitrateof90%wherethecacheaccesstimeis10nsandthememoryaccesstimeis100nsis()(a)55ns(b)45ns(c)90ns(d)19ns10.Delayedbranchingisused()(a)tointroducedelaysinprogramexecution(b)inpipelining(c)incachememory(d)decodinginstructionsPart2—FundamentalsofComputerDesign[10points]1.[10points]Inmanypracticalapplicationsthatdemandareal-timeresponse,thecomputationalworkloadWisoftenfixed.Asthenumberofprocessorsincreasesinaparallelcomputer,thefixedworkloadisdistributedtomoreprocessorsforparallelexecution.Assume20percentofWmustbeexecutedsequentially,and80percentcanbeexecutedby4nodessimultaneously.Whatisafixed-loadspeedup?Part3—InstructionSetArchitecture[20points]2.[8points]Supposethevariablexoftypeintandataddress0x100hasahexadecimalvalue0x01234567.Theorderingofthebyteswithintheaddressrange0x100through0x103dependsonthetypeofmachine.Whatwillbearrangedinmemory0x100~0x103accordingtoLittleEndianandBigEndian?3.[12points]Amodelmachinehas7instructions,whichfrequenciesare43%,21%,12%,8%,6%,6%,and4%respectively.3.1Encodingoperatorwiththeminimumaveragecodelength.3.2Accordingto5.1,givethevalueoftheminimumaveragecodelength.Part4—Pipelining[35points]4.[6points]Whywouldadesignersometimesallowstructuralhazards?5.[21points]Usingthefollowingcodefragment:LOOP:LWR1,0(R2);loadR1fromaddress0+R2ADDIR1,R1,#1;R1=R1+1SW0(R2),R1;storeR1ataddress0+R2ADDIR2,R2,#4;R2=R2+4SUBR4,R3,R2;R4=R3-R2BNEZR4,LOOP;branchtoLOOPifR4!=0AssumetheinitialvalueofR3isR2+200.TheyrunonapipelinedmachinelikeDLX.5.1.Accordingtothefollowingformat,showthetimingofthisinstructionsequencewithnormalforwardingandbypassinghardware.Alsoassumingaregisterreadandawriteinthesameclockcycle“forwards”throughtheregisterfile.instructionClock123456789101112131415LWR1,0(R2)IFIDEXEMEMWBADDIR1,R1,#1SW0(R2),R1ADDIR2,R2,#4SUBR4,R3,R2BNEZR4,LOOP5.2.Assumethatthebranchishandledbypredictingitasnottaken.Ifallmemoryreferencestake1cycle,howmanycyclesdoesthislooptaketoexecute?5.3.Inordertoreducethetotalcyclesof8.2,whatmeasurescouldbetaken?Giveanexplanation.6.[8points]Fortwo-levelbranchpredictionstrategywith(2,2)predictor,howmanybitsdoesthebranchpredictionbufferneedfor2Kbranchinstructions?Part5—MemoryHierarchy[25points]7.[7points]Cachedesign:Giveshortanswerstothefollowingquestions.7.1Cachemissratesdecreasewithlargercacheblocksizesduetowhatkindoflocality?7.2Howmanysetsinfullyassociativecachewith64cacheblocks?7.3Howmanysetsinadirect-mappedcachewith128cacheblocks?7.4Howtokeepthemainmemoryandthecacheconsistent?8.[18points]Assumeafourblocksdirect-mappedcache,twowordsperblock,LRUreplacement.Thecacheisinitiallyempty.Forthewordaddressreferencestream(reads):0,1,12,2,3,4,12,58.1Howmanyoftheseeightreferencesarehits?8.2.Ifthecacheisfullyassociativeinstead,howmanywordaddressreferenceswouldbehits?