用FPGA来实现PCI-E接口原理图

01Xilinx0381219456321REVTITLESCHEM,ML555PCIEPCIPCI-XPCB,1280389SCALESHEETSIZEDWGNO123654BAABCDCDCofDRAWNBYPCIeCEMSpec,Pg.56footnotes:-BydefaultthePETpxandPETnxpinsshallbeconnectedtothePCIExpresstransmitterdifferentialpaironthesystemboard,andthePCIExpressreceiverpairontheadd-incard-BydefaultthePERpxandPERnxpinsshallbeconnectedsystemboard,andthePCIExpresstransmitterpairontheadd-incardtothePCIExpressreceiverdifferentialpaironthe2)PCIEdgeConnectorP1iskeyedas3.3VONLYML555PCB:Notes:1)ActiveLowSignalsNamesendinBor_B3)+IOVforPCIedgeconnectoriswiredto3.3V4)Ref.Sheet6:XilinxPCBSchematicNumber:0381219LatestSchematicsRevision:ProductionRev01forcustomerReleaseML555EngineeringRev04(4theng.spin)willbeRev01_10-30-063710-30-2006_10:431DAVIDNAYLOR01Xilinx0381219456321REVTITLESCHEM,ML555PCIEPCIPCI-XPCB,1280389SCALESHEETSIZEDWGNO123654BAABCDCDCofDRAWNBY10.J5SATAConn,MGTX0Y5SATAI/F,J6-J9SMAConns,U3ClockMux1.ML555SchematicSheetCoverPage2.ML555SchematicSheetList(thispage)3.P1aPCI/PCI-X3.3VEdgeConnector,32-bitportion4.P1bPCI/PCI-X3.3VEdgeConnector,64-bitextension5.PCI/PCI-XP1FPGAI/F,3.0VBanks11,13,156.PCIeEdgeConn.P13,PCIeI/FMGT'sX0Y0,X0Y1,X0Y2,X0Y37.MGTX0Y0,X0Y1,X0Y2,X0Y3Power&Filtering8.SFP1(J3),SFP2(J4)OpticalI/FConnectors9.MGTX0Y4SFP1&2I/F,U2ClockMux11.Y1Osc.125MHzLVDS,U11ClockMux13.U6CPLD,Reset&ProgPush-Buttons17.J15,J162x32EPHYBERGHEADERS,J1USB-BConn,U5USBI/F19.J2200-pin1.8VDDR2SODIMMSocket20.DDR2MemoryTerminationResistors21.Banks17and21DDR2SODIMMSocketI/F22.Banks4and22DDR2SODIMMSocketI/F23.Bank0JTAGandModeI/F28.UnusedXC5VLX110TBanks5,6,23,2527.UnusedMGT'sXC5VLX110T29.VoltageRegulatorsVR1,VR2,VR330.VoltageRegulatorsVR4,U12,U13,U1431.MGTVoltageRegulatorsVR5,VR6,VR732.DecouplingCaps:12V,5V,3.3VML555SchematicSheetList36.ML555VoltageRegulatorTopology37.ML555BlockDiagram33.DecouplingCaps:2.5VVccaux,2.5VVcco26.FPGAPowerConnections:VCCINT1.0V,VCCAUX2.5V,GND35.DecouplingCaps:3.0VPCI,1.0VVccint18.Bank12BERGEPHYI/F,Bank20BERGHDR,U6CPLDI/F24.U8ClockSynthesizer1-MemoryI/F25.U7ClockSynthesizer2-SATAandSFPI/F15.Banks1,2PFI/F,GPIOI/F,USBI/F14.Banks18,19P32,P33GPIOSamtecConnectors34.DecouplingCaps:1.8VDDR2Mem,0.9VDDR2Term12.U1PlatformFlash,P5JTAGConn,Y2Osc33MHzCMOS,U2PCIClkBuffer16.Bank3GCLKI/F,misc.CLKI/F,Y2Osc.200MHzLVPECL,J10&J11Clk.SMA378-30-2006_8:062DAVIDNAYLORPCI_VCCDDVCC3V3VCC5VCC5DD1212123D01Xilinx0381219456321REVTITLESCHEM,ML555PCIEPCIPCI-XPCB,1280389SCALESHEETSIZEDWGNO123654BAABCDCDCofDRAWNBYGNDGND+AUXVPME#M66ENAD[21]GNDKEY-12VKEY+IOV+12VTRST#TMSTDI+5VINTA#INTC#+5VRESERVEDRESERVEDRST#+IOVGNT#GNDAD[30]+3.3VAD[28]AD[26]GNDAD[24]IDSEL+3.3VAD[22]AD[20]GNDAD[18]AD[16]+3.3VFRAME#GNDTRDY#GNDSTOP#+3.3VGNDPARAD[15]+3.3VAD[13]AD[11]GNDAD[09]C/BE#[0]+3.3VAD[06]AD[04]GNDAD[02]AD[00]+IOVREQ64#+5V+5VTCKGNDTDO+5V+5VINTB#INTD#PRSNT1#RESERVEDPRSNT2#KEYKEYRESERVEDGNDCLKGNDREQ#+IOVAD[31]AD[29]GNDAD[27]AD[25]+3.3VC/BE#[3]AD[23]AD[19]+3.3VAD[17]C/BE#[2]GNDIRDY#+3.3VDEVSEL#LOCK#PERR#+3.3VSERR#+3.3VC/BE#[1]AD[14]GNDAD[12]AD[10]AD[08]AD[07]+3.3VAD[05]AD[03]GNDAD[01]+IOVACK64#+5V+5VPCIXCAPSMBCLKSMBDATGNDGNDVCC3V31PCIEDGECONNECTOR3.3V32-bitSECTIONREMOVEJUMPERFOR66MhzEDGE_PRSNT1_BEDGE_PRSNT2_BtoU10LX50TBank5JUMPER2-3=NOTPCI-Xcapable,PCIModeOnlyJUMPER1-2=PCI-X66MHzcapableNOJUMPER=PCI-X133MHzcapableP8JUMPERS:1P6DNAAUXV_A1412R240100R12R239100R12R23815RA1A10A11A14A15A16A17A18A19A2A20A21A22A23A24A25A26A27A28A29A3A30A31A32A33A34A35A36A37A38A39A4A40A41A42A43A44A45A46A47A48A49A5A52A53A54A55A56A57A58A59A6A60A61A62A7A8A9B1B10B11B14B15B16B17B18B19B2B20B21B22B23B24B25B26B27B28B29B3B30B31B32B33B34B35B36B37B38B39B4B40B41B42B43B44B45B46B47B48B49B5B52B53B54B55B56B57B58B59B6B60B61B62B7B8B9B50B51A50A51P1EDGE_PCI_3V3376-8-2006_19:073DAVIDNAYLOR12C130.01UF12C120.01UF12R110K123P812P912P7EDGE_RST_I_BEDGE_RST_BPCIXCAP_PDEDGE_M66ENEDGE_PME_BEDGE_REQ64_BEDGE_ACK64_BEDGE_SERR_BEDGE_PERR_BEDGE_DEVSEL_BEDGE_IRDY_BEDGE_STOP_BEDGE_TRDY_BEDGE_FRAME_BEDGE_REQ_BEDGE_PME_BEDGE_GNT_BEDGE_INTC_BEDGE_INTA_BEDGE_PCIXCAPVCC5VCC5VCC5VCC5VCC5VCC5VCC5VCC5CLK_FROM_EDGEEDGE_AD8EDGE_CBE1EDGE_PCIXCAPEDGE_AD19EDGE_AD12EDGE_M66ENEDGE_CBE2EDGE_CBE3EDGE_CBE0EDGE_AD30EDGE_AD28EDGE_AD26EDGE_AD24EDGE_AD22EDGE_AD20EDGE_AD18EDGE_AD16EDGE_AD31EDGE_AD29EDGE_AD27EDGE_AD25EDGE_AD23EDGE_AD21EDGE_AD17EDGE_AD10EDGE_AD7EDGE_AD5EDGE_AD3EDGE_AD15EDGE_AD13EDGE_AD11EDGE_AD9EDGE_AD6EDGE_AD4EDGE_AD2EDGE_AD0EDGE_JTAGEDGE_AD1EDGE_IDSELEDGE_PAREDGE_AD14EDGE_INTB_BEDGE_INTD_BGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDFPGA_EDGE_PME_BVCC3V3VCC3V3DD+IOVGNDRESERVEDRESERVEDRESERVEDGNDGNDGND+IOVGNDGNDGNDGNDGNDGNDRESERVEDC/BE#[6]C/BE#[4]GNDAD[63]AD[61]AD[59]AD[57]AD[55]AD[53]AD[51]AD[49]+IOVAD[45]GNDC/BE#[7]C/BE#[5]+IOVGNDPAR64AD[47]AD[62]AD[60]GNDAD[58]+IOVAD[56]AD[54]AD[52]AD[50]AD[48]AD[46]AD[44]AD[43]AD[41]AD[39]AD[37]AD[35]AD[33]GNDRESERVEDAD[32]AD[34]AD[36]GNDAD[38]AD[40]+IOVAD[42]01Xilinx0381219456321REVTITLESCHEM,ML555PCIEPCIPCI-XPCB,1280389SCALESHEETSIZEDWGNO123654BAABCDCDCofDRAWNBYPCIEDGECONNECTOR3.3V64-bitEXTENSION375-30-2006_18:444DAVIDNAYLORA63A64A65A66A67A68A69A70A71A72A73A74A75A76A77A78A79A80A81A82B63B64B65B66B67B6