FPGA移相信号发生器程序清单

1一、数字式移相信号发生器程序清单：（1）顶层模块*模块功能:本模块为顶层模块进行顶层映射,实现底层模块的连接*libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitytopisport(clk0:instd_logic;--50MHz基准时钟信号;set0,butt1,butt2:instd_logic;--确定按键,幅值增,减;butt0,sw1_0,sw2_0:instd_logic;--选折开关,量程扩长*10档;data3,data2,data1,data0:instd_logic_vector(3downto0);--拨码盘BCD码输入;lcd:outstd_logic_vector(7downto0);--BCD码输出;shift:outstd_logic_vector(3downto0);--位选信号;dd0,dd1:outstd_logic_vector(7downto0);--控制D/A进行幅度调节;a0,a1:outstd_logic_vector(9downto0));--正弦波幅值输出;endtop;architectureBehavioraloftopiscomponentmove_phasePort(clk4:instd_logic;sw1,sw2:instd_logic;--sign1:instd_logic;--d_4:outstd_logic_vector(7downto0)bcd00_4,bcd10_4,bcd20_4,bcd30_4:inintegerrange0to10;shift_4:outstd_logic_vector(3downto0);lcd_4:outstd_logic_vector(7downto0));endcomponent;componentwave_generatorPort(clk1:instd_logic;f_1:instd_logic_vector(8downto0);d:outstd_logic_vector(7downto0));endcomponent;componentfupin_controlPort(clk2,sw1_2,sw2_2,set_2,butt0_2,butt1_2,butt2_2:instd_logic;--tmp_2:inintegerrange0to9999;data0_2,data1_2,data2_2,data3_2:instd_logic_vector(3downto0);d_2:instd_logic_vector(7downto0);dd0_2,dd1_2:outstd_logic_vector(7downto0);a0_2,a1_2:outstd_logic_vector(9downto0);f_2:outstd_logic_vector(8downto0));endcomponent;componentyimaPort(clk3,set3:instd_logic;2--amp0,amp1:instd_logic;sw1_3,sw2_3:instd_logic;--tmp:inintegerrange0to9999;--tmpp:instd_logic_vector(8downto0);data0_3,data1_3,data2_3,data3_3:instd_logic_vector(3downto0);bcd00_3,bcd10_3,bcd20_3,bcd30_3:outintegerrange0to10);endcomponent;signalbcd0_4,bcd1_4,bcd2_4,bcd3_4:integerrange0to10;signalf_cont:std_logic_vector(8downto0);signald_cont:std_logic_vector(7downto0);beginu1:move_phaseportmap(clk4=clk0,sw1=sw1_0,sw2=sw2_0,bcd00_4=bcd0_4,bcd10_4=bcd1_4,bcd20_4=bcd2_4,bcd30_4=bcd3_4,shift_4=shift,lcd_4=lcd);u2:wave_generatorportmap(clk1=clk0,f_1=f_cont,d=d_cont);u3:fupin_controlportmap(clk2=clk0,sw1_2=sw1_0,sw2_2=sw2_0,set_2=set0,butt0_2=butt0,butt1_2=butt1,butt2_2=butt2,data0_2=data0,data1_2=data1,data2_2=data2,data3_2=data3,d_2=d_cont,dd0_2=dd0,dd1_2=dd1,a0_2=a0,a1_2=a1,f_2=f_cont);u4:yimaportmap(clk3=clk0,set3=set0,sw1_3=sw1_0,sw2_3=sw2_0,data0_3=data0,data1_3=data1,data2_3=data2,data3_3=data3,bcd00_3=bcd0_4,bcd10_3=bcd1_4,bcd20_3=bcd2_4,bcd30_3=bcd3_4);endBehavioral;（1）幅值控制模块libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityfupin_controlisPort(clk2,sw1_2,sw2_2,set_2,butt0_2,butt1_2,butt2_2:instd_logic;d_2:instd_logic_vector(7downto0);data0_2,data1_2,data2_2,data3_2:instd_logic_vector(3downto0);--tmpp_2:instd_logic_vector(8downto0);3dd0_2,dd1_2:outstd_logic_vector(7downto0);a0_2,a1_2:outstd_logic_vector(9downto0);f_2:outstd_logic_vector(8downto0));endfupin_control;architectureBehavioraloffupin_controlissignalsign,sign1:std_logic;signalf0,f1:std_logic_vector(8downto0);signalqq:integerrange0to78125000;signalb:integerrange0to78125000;signaltmpp:std_logic_vector(8downto0);signaltmp:integerrange0to9999;--signald:std_logic_vector(7downto0);signalamp0,amp1:std_logic_vector(9downto0);signalcoun:integerrange0to78125000;beginqq=138889whensign1='0'else13889whensign1='1';process(clk2)variableds:std_logic;beginifrising_edge(clk2)thenifds='1'thenf_2=f0;ds:=notds;dd1_2=d_2;elsef_2=f1;ds:=notds;dd0_2=d_2;endif;endif;endprocess;--qqq=500000whenss=1000else--5000000whenss=0100else--50000000whenss=0010else--50000;process(clk2)variablecount4:integerrange0to6250000;variablecount,cc:integerrange0to78125000;variablecount3:integerrange0to250000000;variablecount1:integerrange0to12500000;variablecount0:integerrange0to3249999;variableddd:std_logic_vector(9downto0);variabledd0,dd1,dd2,dd3,dd4:integerrange0to255;variableadr:integerrange0to63;variablevc:integerrange0to12499999;beginifrising_edge(clk2)thenifsw1_2='0'then--当sw1='0',sw2='1'则幅度调节;4ifsw2_2='1'thenifset_2='1'thenf1=(others='0');f0=(others='0');sign='1';vc:=0;tmpp=conv_std_logic_vector((conv_integer(data2_2)*100+conv_integer(data1_2)*10+conv_integer(data0_2)),9);elseifvc=12499999thenvc:=0;ifbutt1_2='1'theniftmpp101100111thentmpp=tmpp+1;elsiftmpp=101100111thentmpp=101100111;endif;elsifbutt2_2='1'theniftmpp000000000thentmpp=tmpp-1;elsiftmpp=000000000thentmpp=000000000;endif;endif;elsevc:=vc+1;endif;iftmp0thenifcounqqthencoun=coun+tmp;b=b+1;elseifcount=bthencount:=0;iftmpp000000000thenifsign='1'thenf0=tmpp;sign='0';elseiff0=101100111thenf0=000000000;elsef0=f0+1;endif;endif;elseiff0=101100111thenf0=000000000;elsef0=f0+1;endif;endif;iff1=101100111thenf1=000000000;elsef1=f1+1;endif;elsecount:=count+1;endif;endif;endif;endif;elseifbutt0_2='1'thenifset_2='1'then5sign1='1';tmp=conv_integer(data3_2)*1000+conv_integer(data2_2)*100+conv_integer(data1_2)*10+conv_integer(data0_2);coun=0;b=0;amp0=0111111111;amp1=0111111111;f0=000000000;f1=000000000;endif;elseifset_2='1'thentmp=conv_integer(data3_2)*1000+conv_integer(data2_2)*100+conv_integer(data1