物理学院本科论文答辩ppt

基于FPGA的逻辑分析仪的设计指导老师：答辩人：xxx大学物理学院xx级本科论文答辩需求分析1硬件设计2逻辑设计3时序分析4架构需求分析FPGA外界输入VGA按键控制逻辑分析仪的设计方案湖南科技大学物理学院2007级电子信息科学与技术1班唐德硬件设计电源设计VCCINT117VCCINT64VCCINT46VCCINT135VCCIO129VCCIO444VCCIO2115VCCIO2137VCCIO381VCCIO18VCCIO3102VCCIO466U5FEP1C3T144C8VCC3.3VCC1.5GND116GND138GND101GND80GND65GND43GND118GND136GND63GND9GND30GND45U5GEP1C3T144C8GNDGND0.1uFC210uFC1D1SS14SW1POWER_LED1KR1GNDVCC5123J1PWR2.5GNDVCCVin3Vout2GND1U2LTI086CM-3.3V10uFC2110uFC230.1uFC220.1uFC24Vin3Vout2GND1U3LTI086CM-1.5VGNDVCC5VCC3.3VCC1.5VCCA_PLL115GNDA_PLL118GNDG_PLL119U5HEP1C3T144C8FB110uFC30.1uFC40.001uFC5VCC1.5GND0.1uFC60.1uFC70.1uFC80.1uFC90.1uFC100.1uFC110.1uFC120.1uFC130.1uFC150.1uFC160.1uFC170.1uFC180.1uFC1910uFC2010uFC14GNDGND湖南科技大学物理学院2007级电子信息科学与技术1班唐德下载设计DATA013nCONFIG14nCEO20nCE21MSEL022MSEL123DCLK24CONF_DONE86nSTATUS87TCK88TMS89TDO90TDI95U5EEP1C3T144C810KR410KR510KR6RE_COF1GNDVCC3.3GNDTDITDOTCKTMSDCLKDATAnCEnCEOnCONFIGnSTATUSCONF_DONEVCC3VCC7VCC8DATA2DCLK6nCS1ASDI5GND4U4EPCS1SI8GNDVCC3.3DATADCLKnCSASDI12345678910U7EPCS_JTAG10KR7DCLKCONF_DONEnCONFIGDATAASDInCEnCSOGNDGNDVCC3.312345678910U8FPGA_JTAG10KR810KR910KR10TCKTDOTMSTDIVCC3.3VCC3.3GND湖南科技大学物理学院2007级电子信息科学与技术1班唐德时钟设计CLK0EN1GND2OUT3VCC4U150MHZ33R20.1uFC25CLK2EN1GND2OUT3VCC4U624MHZ33R30.1uFC26CLK3,LVDSCLK2n92CLK2,LVDSCLK2p93CLK0,LVDSCLK1p16CLK1,LVDSCLK1n17U5IEP1C3T144C8CLK0CLK1CLK2CLK3湖南科技大学物理学院2007级电子信息科学与技术1班唐德SDRAM设计VDD1DQ02VDDQ3DQ14DQ25VSSQ6DQ37DQ48VDDQ9DQ510DQ611VSSQ12DQ713VDD14LDQM15WE16CAS17RAS18CS19BA020BA121A10/AP22A023A124A225A326VDD27VSS28A429A530A631A732A833A934A1135A1236CKE37CLK38UDQM39NC/RFU40VSS41DQ842VDDQ43DQ944DQ1045VSSQ46DQ1147DQ1248VDDQ49DQ1350DQ1451VSSQ52DQ1553VSS54U9K4S511632B-TL754.7KR144.7KR134.7KR124.7KR114.7KR15SD_A0SD_A1SD_A2SD_A3SD_A4SD_A5SD_A6SD_A7SD_A8SD_A9SD_A10SD_A11SD_A12SD_DQ0SD_DQ1SD_DQ2SD_DQ3SD_DQ4SD_DQ5SD_DQ6SD_DQ7SD_DQ8SD_DQ9SD_DQ10SD_DQ11SD_DQ12SD_DQ13SD_DQ14SD_DQ15SD_CLKSD_BA0SD_BA1SD_CSSD_WESD_CASSD_RASVCC3.3VCC3.3GNDGND0.1uFC270.1uFC280.1uFC290.1uFC30VCC3.3GND湖南科技大学物理学院2007级电子信息科学与技术1班唐德VGA接口设计470R281KR29470R301KR312KR32470R331KR372KR38123456789101112131415U11VGAGND75R3475R3575R36HYSNCVYSNCRGB_R0RGB_R1RGB_R2RGB_G0RGB_G1RGB_G2RGB_B0RGB_B1湖南科技大学物理学院2007级电子信息科学与技术1班唐德按键设计12345678161514131211109S2SWDIP-8S1S3S4S54.7KR194.7KR184.7KR174.7KR16VCC3.3GNDKEY1KEY2KEY3KEY44.7KR264.7KR244.7KR224.7KR204.7KR274.7KR254.7KR234.7KR21VCC3.3SW01SW02SW03SW04SW05SW06SW07SW08GND湖南科技大学物理学院2007级电子信息科学与技术1班唐德BANK2IO,LVDS5p(DEV_CLRn)144IO,LVDS5n(DEV_OE)143IO,LVDS6p(DQ0T7)142IO,LVDS6n(DQ0T6)141IO,LVDS7p(DQ0T5)140IO,LVDS7n(DQ0T4)139IO,DPCLK2(DQS1T)134IO,VREF2B2133IO132IO,LVDS8p131IO,LVDS8n130IO,LVDS9p129IO,LVDS9n128IO,LVDS10p127IO,LVDS10n126IO,VREF1B2125IO,LVDS11p124IO,LVDS11n(DM0T)123IO,LVDS12p122IO,LVDS12n121IO,VREF0B2120IO,DPCLK3(DQS0T)119IO,LVDS13p(DQ0T3)114IO,LVDS13n(DQ0T2)113IO,LVDS14p(DQ0T1)112IO,LVDS14n(DQ0T0)111IO,LVDS15p110IO,LVDS15n109U5BEP1C3T144C8BANK4IO,LVDS23n72IO,LVDS23p71IO,LVDS24n(DQ1B0)70IO,LVDS24p(DQ1B1)69IO,LVDS25n(DQ1B2)68IO,LVDS25p(DQ1B3)67IO,DPCLK6(DQS0B)62IO,VREF0B461IO,LVDS26n60IO,LVDS26p59IO,LVDS27n58IO,LVDS27p(DM1B)57IO,VREF1B456IO,LVDS28n55IO,LVDS28p54IO,LVDS29n53IO,LVDS29p52IO,LVDS30n51IO,LVDS30p50IO49IO,VREF2B448IO,DPCLK7(DQS1B)47IO,LVDS31n(DQ1B4)42IO,LVDS31p(DQ1B5)41IO,LVDS32n(DQ1B6)40IO,LVDS32p(DQ1B7)39IO,LVDS33n38IO,LVDS33p37U5DEP1C3T144C811223344556677889910101111121213131414151516161717181819192020U12HEADER10X2SD_A0SD_A1SD_A2SD_A3SD_A10SD_DQ0SD_DQ1SD_DQ2SD_DQ3SD_DQ4SD_DQ5SD_DQ6SD_DQ7PIN109PIN110PIN111PIN112PIN113PIN114PIN119PIN120PIN121PIN122PIN123PIN124PIN125PIN126PIN127PIN128DS_STCPDS_DATADS_SHCPRST_nVGA_R0VGA_G0VGA_G1VGA_G2VGA_B0VGA_B1VYSNCHYSNCKEY1KEY2KEY3KEY4TI_INRI_OUTSPI_CLKSPI_MISOSD_BA0SD_BA1SD_CSSD_RASSD_CASPIN109PIN110PIN111PIN112PIN113PIN114PIN119PIN120PIN121PIN122PIN123PIN124PIN125PIN128GNDGNDVCC3.3VCC1.5BANK1IO,LVDS0n36IO,LVDS0p(DQ1L7)35IO,LVDS1n(DQ1L6)34IO,LVDS1p(DQ1L5)33IO(DQ1L4)32IO,VREF2B131IO,DPCLK0(DQS1L)28IO,PLL1_OUTn27IO,PLL1_OUTp26IO(ASDO)25IO(nCSO)12IO,VREF1B111IO,DPCLK1(DQS0L)10IO,LVDS2n(DQ1L3)7IO,LVDS2p(DQ1L2)6IO,VREF0B15IO,LVDS3n4IO,LVDS3p(CLKUSR)/(DQ1L1)3IO,LVDS4n(CRC_ERROR)/(DQ1L0)2IO,LVDS4p(INIT_DONE)/(DM1L)1U5AEP1C3T144C8BANK3IO,LVDS16p108IO,LVDS16n107IO,LVDS17p106IO,LVDS17n105IO,VREF0B3104IO(DQ1R0)103IO,DPCLK4(DQS0R)100IO,LVDS18p(DQ1R1)99IO,LVDS18n(DQ1R2)98IO(DQ1R3)97IO,VREF1B396IO94IO91IO(DM1R)85IO,LVDS19p(DQ1R4)84IO,LVDS19n(DQ1R5)83IO,DPCLK5(DQS1R)82IO,VREF2B379IO,LVDS20p(DQ1R6)78IO,LVDS20n(DQ1R7)77IO,LVDS21p76IO,LVDS21n75IO,LVDS22p74IO,LVDS22n73U5CEP1C3T144C8SD_A4SD_A5SD_A6SD_A7SD_A8SD_A9SD_A11SD_CLKSD_CKEASDInCSOSD_DQ8SD_DQ9SD_DQ10SD_DQ11SD_DQ12SD_DQ13SD_DQ14SD_DQ15SD_WEPIN100PIN103PIN104PIN105PIN106PIN107PIN108PIN96PIN97PIN98PIN99SW01SW02SW03SW04SW05SW06SW07SW08VGA_R1VGA_R211223344556677889910101111121213131414151516161717181819192020U10HEADER10X2PIN96PIN97PIN98PIN99PIN100PIN103PIN104PIN105PIN106PIN107PIN108GNDGNDVCC3.3VCC1.5扩展接口设计湖南科技大学物理学院2007级电子信息科学与技术1班唐德逻辑设计采样显示触发控制存储逻辑分析仪设计方案湖南科技大学物理学院2007级电子信息科学与技术1班唐德VGA显示模块Display_Module系统控制部分System_Module采样控制模块Sampling_ModuleFPGA湖南科技大学物理学院2007级电子信息科学与技术1班唐德