Cadence-实验系列13-RTL编译和束缚-RC-and-EC

Cadence实验系列13_RTL编译和束缚_RTLcompiler&Encounterconformal2010.12.23RTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowIntroductionRCisafast,highcapacitysynthesissolutionfordemandingchipdesigns‘Globalfocusedsynthesis’resultsinrapidtimingclosureIntroduction综合是前端设计的重要步骤HDL代码翻译成门级网表netlist约束条件（达到面积，时序等参数标准）需特定工艺库评价标准：面积，速度，功耗SynthesistoolIC设计综合工具包括SynopsisDC和CadenceRC；在FPGA端，常用的综合工具有Synplicitysynplify和XilinxXSTSynthesis综合的过程分为两步，首先将HDL描述语言翻译成与工艺库无关的门级网表文件，然后通过综合工具优化，映射到跟具体工艺库相关的门级网表。RTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowRoleinICdesign前端设计规格制定详细设计HDL编码仿真验证逻辑综合ICprocessAdvantage时序收敛的全局综合工具提高芯片性能缩短设计时间提供高质量的硅片（Qos）RTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowStartGUI命令符：rc-guiGeneralViewManubarLogicalviewerHDLviewerSchematicviewerPhysicalviewerManubarManubarLogicalviewerandHDLvewerSchematicviewerRTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowSynthesisflowInvoketheRCSpecifythelibraryLoadHDLfilesPerformElaborationApplyconstraintsSynthesizeSavedesignAnalyzeSynthesisflowset_attributelib_search_pathfull_path_of_technology_library_directory/set_attributehdl_search_pathfull_path_of_hdl_files_directoryset_attributelibrarytechnology_library/read_hdlhdl_file_nameselaboratetop_level_design_namesetclock[define_clock–periodperiodicity–nameclock_name[clock_ports]]external_delay–inputspecify_input_external_delay_on_clockexternal_delay–outputspecify_output_external_delay_on_clocksynthesize-to_mappedreporttimingspecify_timing_report_file_namereportareaspecify_area_report_file_namewrite–mappedspecify_netlist_namewrite_scriptscript_file_nameStep1InvoketheRCrc－guiStep2Specifythelibrary设置工艺库存放路径set_attributelib_search_path/export/home1/STSY_BB/BB_y29/lib/Synopsys指定要加载的工艺库set_attributelibrary{hjtc18_tt.lib}Step3LoadHDLfilesLoadMipssourcesread_hdl/export/home1/STSY_BB/BB_y29/mips_source/MCore.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/alu_v2.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/biu.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/branch.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/core.vread_hdl…….tclscriptStep4PerformElaborationBuildsdatastructuresInfersregistersinthedesignPerformshigher-levelHDLoptimization,suchasdeadcoderemovalCheckssemanticsStep4PerformElaborationElaborate建立一个结构级描述，该描述与工艺无关SchematicviewerStep5ApplyConstraintsConstraintCommandsdefine_clock定义时钟输入波形external_delay设定输入输出相对时钟的延时path_delay设置路径时序约束其他：create_mode,define_cost_groud,multi_cycleStep6SynthesizesetMAP_EFFhighsynthesize-to_mappedeff$MAP_EFF-no_incrStep7Savedesign保存综合的网表文件write-mappedMCore_synth.v保存约束文件（sdc）write_sdcMCore_tst.sdcStep8Analyze输出功耗报表文件reportpowerMCore.power.rpt输出时序报表文件reporttimingMCore.timing.rptStep8Analyzetimingandpowertclscript--命令行批量处理set_attributelib_search_path/export/home1/STSY_BB/BB_y29/lib/Synopsys##Thisdefinesthelibrariestouseset_attributelibrary{hjtc18_tt.lib}read_hdl/export/home1/STSY_BB/BB_y29/mips_source/MCore.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/alu_v2.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/biu.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/branch.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/core.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/cp0.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/decode.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/exec.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/fifo.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/idtlb.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/irq.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/jtlb.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/mcore_define.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/mdu_v2.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/mem_stage.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/mmu.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/pag.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/pipeline.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/reg_ctrl.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/regfile.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/shifter.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/tlb.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/tlb_page.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/trap.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/write_back.vtclscript##Thisbuilsthegeneralblocekelaborate##thisallowsyoutodefineaclockandthemaximumallowabledelays##READMOREABOUTTHISSOTHATYOUCANPROPERLYCREATEATIMINGFILEdefine_clock-nameclk-period5000[find/-portclk]external_delay-input100-clock[find/-clockclk]-edge_fall[all_inputs]external_delay-output100-clock[find/-clockclk]-edge_fall[all_outputs]set_attributewireload_modeenclosedset_attributemax_dynamic_power0.0MCoreset_attributemax_leakage_power0.0MCore##ThissynthesizesyourcodesetMAP_EFFhighsynthesize-to_mapped-eff$MAP_EFF-no_incr##Thiswritesallyourfiles##cha