4数字电子基础-组合逻辑电路

本章内容组合逻辑电路的分析与设计常用中规模集成电路南京大学金陵学院—肇莹组合逻辑电路组合逻辑电路输入逻辑变量输出逻辑变量Output=Function(Input)组合逻辑电路的分析BDCDBDCDYACDBCDCBDACDBCDCBDYDBADCDBADCY012组合逻辑电路设计输入DCBAY2Y1Y0输出0000000100100011010001010110011110001001101010111100110111101111001001001001001001010010010010010100100100100100组合逻辑电路设计设计一个3位奇偶校验电路，当输入变量中有奇数个“1”时，输出为“1”,否则，输出为“0”.用与非门来实现。ABCF00000101001110010111011101111000ABCCBACBACBAF组合逻辑电路设计111101ABC00011011ABCCBACBACBAABCCBACBACBAF&&&&&&&&ABCF组合逻辑电路设计组合逻辑电路设计RAGZ00000110001001110111011110010111RAGGRAGARAGRGARZ组合逻辑电路设计AGRGRAGARZ组合逻辑电路设计AGRGRAGARZ译码器用二极管组成的译码器VVVVILIH0,3译码器3-to-8译码器74LS1381GAG2BG2ABC0Y1Y2Y3Y4Y5Y6Y7YG1ABCY0Y1Y2Y3Y4Y5Y6Y774x13815141312111097645123Pin-8isGNDPin-16isVCCCBAGGGYBA)(2210CBAGGGYBA)(2211CBAGGGYBA)(2217表示低电平有效译码器AG2BG2译码器4线-16线译码器译码器的应用用译码器来实现逻辑函数。当译码器在工作状态下CBAY0CBAY1CBAY711,022GGGBA译码器的应用例6,5,3,0,,mZYXFG1G2AG2BABCY0Y1Y2Y3Y4Y5Y6Y774x138151413121110976451236530,,YYYYZYXF&100XYZ二——十进制译码器74LS42七段显示译码器BS201A灭零输入端：灭灯输入/灭零输出：74x48A3A2A1A0abcdefg00001001LTRBOBI/RBI七段显示译码器aYbYcYdYeYfYgY.1~,0gaYYthenLTifRBI灯测试端：LT.0~,0000&00123gaYYthenAAAARBIifRBOBI/.0~,0gaYYthenBIifRBILTAAAARBO0123七段显示译码器七段显示译码器编码器RequestEncoderREQ1REQ2REQ3REQNRequestor’snumber优先权编码器74x14874x148EII7I6I5I4I3I2I1I0A2A1A0GSEO54321131211106791415EOInputOutputEII0I1I2I3I4I5I6I7A2A1A0GS1000000000XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX00XXX00000011111111111111111111111111111111111111111100000011001010011101001010110110101111011101EI----EnableGS---表示编码器工作，并且有编码信号输入(GotSometing)EO---表示编码器工作，但是没有编码信号输入。74x148EII7I6I5I4I3I2I1I0A2A1A0GSEO54321131211106791415EII7I6I5I4I3I2I1I0A2A1A0GSEO5432113121110679141516线-4线编码器Request15Request14Request13Request12Request11Request10Request9Request8Request7Request6Request5Request4Request3Request2Request1Request0&&&A3A2A1A0数据选择器101130112011101101SAADAADAADAADY201230122012101202SAADAADAADAADY74x153数据选择器ENABCD0D1D2D3D4D5D6D7YY74x15171110493211514131256ENDABCDCBADCBAY710数据选择器的扩展ENABCD0D1D2D3D4D5D6D7YENABCD0D1D2D3D4D5D6D7YAY0Y1ENBC扩展位数数据选择器的应用用数据选择器来实现逻辑函数ABCBABCAL01CBACBACBACBACABABCCBABCACABABCCBABCACCABCBABCAL0,142106753DDDDDDDDENABCD0D1D2D3D4D5D6D7YY74x1517111049321151413125600001111试用4选1数据选择器来实现数值比较器+ABBAL1BAL3BAL21位数值比较器BABAL1BAABBABABAL3BABAL2如何比较01230123&BBBBAAAA00112233&&&&BABABABA数值比较器(74x85)001122331122332233331BABABABABABABABABABABAL001122331122332233332BABABABABABABABABABABAL001122333BABABABABALBAIBABABABA00112233BAIBABABABA00112233BAI数值比较器(74x85)A0B0A1B1A2B2B3A3)(BAI)(BAI)(BAI)(BAL)(BAL)(BAL74x8523410912111314151765数值比较器(74x85)[注意]:当只比较两个四位二进制数时，1,0)()()(BABABAIII0707&YYXXCompare例:+5VYXYXYXX0Y0X1Y1X2Y2X3Y3X4Y4X5Y5X6Y6X7Y4A0B0A1B1A2B2B3A3)(BAI)(BAI)(BAI)(BAL)(BAL)(BAL74x85A0B0A1B1A2B2B3A3)(BAI)(BAI)(BAI)(BAL)(BAL)(BAL74x85数值比较器(CC14585)数值比较器(CC14585))()()()(BABABABAIYYY00112233112233223333BABABABABABABABABABABAYBAIBABABABA0011223300112233BABABABABAYBAI半加器XY00011011Cout00010110SXY0011S11YXYXYXSCoutXY00111XYCoutXYCoutS全加器全加器的真值表ABCin0100011110SABCin0100011110Cout1111inCBAS1111inCBAABC?Cin是进位输入信号Cout是进位输出信号ABCin000CoutS0001011000101001110010111011101101011全加器称作进位传输信号称作进位产生信号中，在BAABCBAABCinABCoSFA全加器逻辑符号CiABiCOCSPG进位传输信号Propagate进位产生信号Generate全加器如何设计4-bit全加器?ABCoSFACiABCoSFACiABCoSFACiABCoSFACi0C0A1A2A3A3B2B1B0B1C2C3C0S1S2S3SCOUT超前进位加法器iiiiiiiiiCPGCBABAC1对于四位二进制数的加法，000000001CPGCBABAC001011111111112CPPGPGCPGCBABAC0012012122222222223CPPPGPPGPGCPGCBABAC001231123223233333333334CPPPPGPPPGPPGPGCPGCBABAC74x28374x283C0A0B0A1B1A2B2A3B3S0S1S2S3C474x283C0C0A0B0A1B1A2B2A3B3S0S1S2S3C474x283A0B0A1B1B2B3A2A3B7B6B5B4A7A6A5A4C8S[3:0]S[7:4]如何实现8位二进制数的加法？组合逻辑电路中的竞争冒险现象&&+XYZZZXYZF10ZZ假设X=Y=1YZZXF0型冒险1,1ZZFYXWhen组合逻辑电路中的竞争冒险现象AAALAAL1型冒险稳定状态下0AAL消除竞争冒险现象的方法YZZXFZXY000111100111111,11ZZFXYWhenXYYZZXFZXZY存在0型冒险消除竞争冒险现象的方法WXYZ00000111100111101111111111WYZWZYXFWXYZ00000111100111101111111111YYFWXZWhen,110ZWXYZYXWWYZWZYXFWWFYZWhen,11ZZFWXYWhen,010存在0型冒险组合逻辑电路设计设计一个组合逻辑电路，实现两个一位二进制数的加法和减法运算。(1)用门电路实现；(2)用3-to-8译码器实现MABCICOS00000001001000110100010101100111100010011010101111001101111011110001011001101000111110110100001115,11,10,9,7,6,5,3mCO15,12,10,9,7,4,2,1mS组合逻辑电路设计组合逻辑电路设计MABCI000111100001111011111111SMABCI000111100001111011111111COAMCBBCCBAMCBAMBCBAMCAMABMACMBCCOIIIIIIIIIIIIICBACBAABCCBACBASMABCIS组合逻辑电路设计G1G2AG2BABCY0Y1Y2Y4Y5Y6Y3Y7G1G2AG2BABCY0Y1Y2Y4Y5Y6Y3Y711Y15Y8Y7Y0例：设计一个函数发生器电路，它的功能表如下表所示，要求：YSS0100A+B01AB10BA11BA组合逻辑电路设计（1）用卡诺图法写出函数Y的最简与或表达式；（2）用一个8选1数据选择器74LS151实现；（3）用两个3线——8线译码器74LS138实现；（可以附加适当的门电路）YBASS010000000011001010011101000010100110001111100011001010100101111100011011111011111014,13,11,8,7,3,2,1imYi01SSAB000111100001111011111