基于VHDL语言的8位RISC-CPU的设计-终稿

毕业设计说明书基于VHDL语言的8位RISC-CPU的设计学院：专业：学生姓名：学号：指导教师：201年月中文摘要I摘要RISC即精简指令集计算机（ReducedInstructionSetComputer）的缩写。RISC-CPU与一般的CPU相比，通过简化指令系统使计算机的结构更加简单合理，从而提高了运算速度。本文对RISC-CPU的架构进行了分析，并使用VHDL语言设计了8位RISC-CPUIP软核。RISC-CPU由八大基本模块构成：时钟发生器、指令寄存器、累加器、算术逻辑单元、数据输出控制器、地址多路器、程序计数器、状态控制器。本设计中借助MAX+PLUSⅡ软件平台对各模块进行时序仿真，并最终给出了指令执行的仿真波形，验证了CPU的功能。设计仿真结果表明，该8位RISC-CPU能够完成既定的任务指标，而且在运行效率上有一定程度改善。关键词：RISC-CPU、VHDL、MAX+PLUSⅡ、IP软核、时序仿真AbstractIIAbstractRISCreducedinstructionsetcomputerthat(ReducedInstructionSetComputer)acronym.RISC-CPUandCPUingeneralcomparedtoinstructionbysimplifyingthestructureofthecomputerismoresimpleandreasonable,therebyincreasingprocessingspeed.Inthispaper,RISC-CPUarchitectureisanalyzed,andbyusingtheVHDLlanguage,Idesignedan8-bitRISC-CPUIPsoftcore.RISC-CPUisbasedon8modules:clockgenerator,instructionregister,accumulator,arithmeticlogicunit,dataoutputcontroller,addressmultiplexer,programcounter,statecontroller.Inthedesign,eachmodulearetimingsimulatedonMAX+PLUSⅡsoftwareplatform,andfinallythesimulatedwaveformofinstructionexecutionthatverifiestheCPUfeaturesisgiven.Designandsimulationresultsshowthatthe8-bitRISC-CPUcancompletethetasks,andalsohasacertaindegreeofimprovementonoperationalefficiency.Keywords:RISC-CPU,VHDL,MAX+PLUSⅡ,IPsoftcore,TimingSimulation目录III目录摘要...............................................................................................................................................IABSTRACT（英文摘要）......................................................................................................II目录.............................................................................................................................................III第一章引言................................................................................................................................11.1课题背景与发展现状.....................................................................................................11.1.1课题背景....................................................................................................................11.1.2RISC-CPU的发展现状...........................................................................................11.2RISC-CPU优势与现实意义.........................................................................................11.2.1RISC-CPU具备的优势...........................................................................................11.2.2本课题的现实意义..................................................................................................21.3本设计的主要内容..........................................................................................................2第二章RISC-CPU的架构设计.............................................................................................32.1RISC-CPU基本架构.......................................................................................................32.2RISC-CPU模块的划分...................................................................................................4第三章八位RISC-CPU各模块设计与仿真.....................................................................63.1时钟发生器.......................................................................................................................63.2指令寄存器.......................................................................................................................73.3累加器..............................................................................................................................103.4算术逻辑单元.................................................................................................................113.5数据输出控制器............................................................................................................133.6地址多路器.....................................................................................................................143.7程序计数器.....................................................................................................................153.8状态控制器.....................................................................................................................17第四章RISC-CPU的综合及操作时序..............................................................................254.1RISC-CPU各模块综合.................................................................................................254.2CPU复位启动操作时序...............................................................................................29结论..............................................................................................................................................30目录IV参考文献.....................................................................................................................................31致谢..............................................................................................................................................32第一章引言-1-第一章引言1.1题背景与发展现状1.1.1课题背景CPU是CentralProcessingUnit——中央处理器的缩写，它是计算机中最重要的一个部分。CPU由运算器和控制器组成，其内部结构归纳起来可以分为控制单元、逻辑单元和存储单元三大部分，这三个部分相互协调，便可以进行分析，判断、运算并控制计算机各部分协调工作。CPU从最初发展至今已经