基于FPGA的串口控制器设计中英文翻译

英文原文TheserialcontrollerdesignbasedonFPGAIntroductionTheuseofhardwaredescriptionlanguage(HDL)isbecomingamoredominantfactor,whendesigningandverifyingFPGAdesigns.Theuseofbehaviorleveldescriptionnotonlyincreasesthedesignproductivity,butalsoprovidesuniqueadvantagesinthedesignverification.ThemostdominantHDLstodayarecalledVerilogandVHDL.ThisapplicationnotewillillustratetheuseofVerilogindesignandverificationofadigitalUART(UniversalAsynchronousReceiver&Transmitter).DefiningtheUART.TheUARTconsistsoftwoindependentHDLmodules.Onemoduleimplementsthetransmitter,whiletheothermoduleimplementsthereceiver.Thetransmitterandreceivermodulescanbecombinedatthetoplevelofthedesign,foranycombinationsoftransmitterandreceiverchannelsrequired.Datacanbewrittentothetransmitterandreadoutfromthereceiver,allthroughasingle8bitbi-directionalCPUinterface.Addressmappingforthetransmitterandreceiverchannelscaneasilybebuildintotheinterfaceatthetoplevelofthedesign.Bothmodulesshareacommonmasterclockcalledmclkx16.Withineachmodulemclkx16aredivideddowntoindependentbaudrateclocks.UARTfunctionaloverview.AbasicoverviewoftheUARTisshownbelow.Atthelefthandsideisshown“transmitholdregister”,“transmitshiftregister”andthetransmitter“controllogic”block,allcontainedwithinthetransmittermodulecalled“txmit”.Attherighthandsideisshownthe“receiveshiftregister”,“receiveholdregister”andthereceiver“controllogic”block,allcontainedwithinthereceivermodulecalled“rxcver”.Thetwomoduleshaveseparateinputsandoutputsformostoftheircontrollines,onlythebi-directionaldatabus,masterclockandresetlinesaresharedbybothmodules.TheUARTstandarddataformat.Infigure3isshowntheUARTserialdataformat.Serialdataarecontainedwithinframesof8databits,aswellascodedinformationbits.Betweensuccessivetransmissions,thetransmissionlineisheldhigh.Atransmissionisinitializedbyaleadinglowstartbit.Nexttotheleadinglowstartbitcomes8bitsofdatainformation,beginningwiththeLSBandafterwardsrepresentedatincreasingsignificanceorderuptotheMSB.Nexttothe8databitscomestheparitybit,representingtheparityresultofthe8databits.Theparitybitcanbeencodedtruebasedonevenparityoroddparitymode.Nexttotheparitybitcomesatrailinghighstopbitindicatingtheendofadataframe..UARTtimingdiagrams.Belowisshown,howdatawrittentothe“transmitholdregister”getsloadedintothe“transmitshiftregister”,andattherisingedgeofthebaudrateclock,shiftedtotxoutput.Belowisshown,howdatagetsshiftedfromrxinputtothe“receiveshiftregister”,andafterwardsloadedintothe“receiveholdregister”.Finallythereceiverraises“rxrdy”flag.TheTransmittermodule.Themasterclockcalledmclkx16aredivideddowntotheproperbaudratecalledtxclkandequalstomclkx16/16.Datawritteninparallelformattothemodulearelatchedinternally,andshiftedinserialformattothetxoutputatthefrequencyofthebaudrateclock.DatashiftedtothetxoutputfollowstheUARTdataformatshowninfig.3.Behavioraldescriptionofthetransmitter.Thetransmitterwaitsfornewdatatobewrittentothemodule.Whennewdataarewrittenatransmitsequenceisinitialized.Datathatwaswritteninparalleltothemodulegetstransmittedasserialdataframesatthetxoutput.Whennotransmitsequenceareinplace,thetxoutputisheldhigh.Implementationofthetransmittermodule.CreatinglogicinVerilogstartswiththemoduleportdeclaration.Heredefinessignals,thatareportedtoandfromthemodule.Nodirectionarespecifiedatthispoint.Nexttoportdefinitionscomesportdirections.Directionsarespecifiedasinput,outputorinout(bidirectional),andcanbereferredtointable1.Nexttothespecificationofportdirectionscomesdeclarationofinternalsignals.InternalsignalsinVerilogaredeclaredas“wire”or“reg”datatypes.Signalsofthe“wire”typeareusedforcontinuosassignments,alsocalledcombinatorialstatements.Signalsofthe“reg”typeareusedforassignmentswithintheVerilog“always”block,oftenuseforsequentiallogicassignments,butnotnecessarily.ForfurtherexplanationseeaVerilogreferencebook.Datatypesoftheinternalsignalsofthemodulecanbereferredtointable3.Wehavenowpassedbyallnecessarydeclarations,andarenowreadytolookattheactualimplementation.Usinghardwaredescriptionlanguageallowsustodescribethefunctionofthetransmitterinamorebehavioralmanner,ratherthanfocusonit’sactualimplementationatgatelevelInsoftwareprogramminglanguage,functionsandproceduresbreakslargerprogramsintomorereadable,manageableandcertainlymaintainablepieces.TheVeriloglanguageprovidesfunctionsandtasksasconstructs,analogoustosoftwarefunctionsandprocedures.AVerilogfunctionandtaskareusedastheequivalenttomultiplelinesofVerilogcode,wherecertaininputsorsignalsaffectscertainoutputsorvariables.Theuseoffunctionsandtasksusuallytakesplacewheremultiplelinesofcodearerepeatedlyusedinadesign,andhencemakesthedesigneasiertoreadandcertainlymaintain.AVerilogfunctioncanhavemultipleinputs,butalwayshaveonlyoneoutput,whiletheVerilogtaskcanhavebothmultipleinputs,andmultipleoutputsandeveninsomecases,nonofeach.BelowisshowntheVerilogtask,thatholdallnecessarysequentialstatements,todescribethetransmitterinthe“shift”mode.Wehereseethetwotagbitscalledtag1andtag2concatenatedtothe“transmitshiftregister.Similartaskswerecreatedtodescribethetransmitterin“idle”and“load