开关电源MOS基础及功耗设计

•MOSFETTechnologies•Packaging•Silicon•MOSFETLosses(SynchronousBuckConverter)•Ideal(noparasiticinductance)vs.non-ideal(inductance)•TCADsimulations•GateandSourceInductance•IntegratedSchottky(SyncFETTM)•CGDxdVDS/dtturn-on(gatebounce)•Cross-conductionduetoMOSFETgateoverlap3KeyMOSFETParameters•Lowon-stateresistance–RDS(ON)•LowQG(TOT)(andQGD)xRDS(ON)Figure-Of-Merit(FOM)•LowInternalGateResistance(RG)•LowPackageInductance(LSOURCE,LGATE,LDRAIN)•LowThermalResistance(RΘJAandRΘJC)•RobustAvalanche(UIS)andLinearModeOperation(FBSOA)0123456199820032008YearIntroducedPackagedRDSON(mΩ)VGS=10V050100199820032008YearIntroducedFOMQGDxRDS(ON)VGS4.5V10V0100200300199820032008YearIntroducedFOM(QTOTALxRDSON)10VRDSONxQTOT(10)4.5VRDSONxQTOT(4.5)30VMOSFETpackagedinSO-8compatiblefootprint4UnclampedInductiveSwitching(UIS)VGATEVDDLLOADVDSIDSRGDUTUnclampedInductiveSwitching(UIS)1101001000100100010000100000100000010000000Timeinavalanche(us)StartingAvalancheCurrent,IAS(A)25Cmeasured25Crating150Cmeasured150CratingIASVDS~BVDSSx1.3VDStAVVGS5AvalancheModesTYPE1(1stquadrantavalanche–testusesparallelswitchwithBVDSSDUT)VGATEVDDLLOADVDSIDSRGDUTVDDLLOADVDSIDSRGDUTLGATEVDDLLOADVDSIDSRGDUTTYPE2(1stquadrantavalanche–DUTswitchesloadinductor)IASVDS(DUT)tAVVGS(DUT)TYPE3(3rdquadrantavalanche-diodetRRtestcircuitusingacontrolledamountofunclampedinductance)ShorttimeperiodwherethedeviceisinavalanchewithVGSVTH(linearmodeoperation)andVDSBVDSS(technicallyoperatingoutsideoftheratedFBSOAarea).AwelldesignedMOSFETwillshownodifferenceinUIScapabilityforthetype1andtype2modes.5Parallelswitchusedtochargeloadinductor.BVDSSofthisswitchisDUTBVDSS.IASVDSVDSVDStAVVGSIDSNote:VDSrisetimeisexaggeratedDUTVGS=0volts(gatehardshortedtosourcethroughRG)IASVDStAVVGS(switch)IDS(DUT)VGSLDInthismode,theMOSFETentersavalancheduringadiodereverserecoveryevent.DiodereverserecoverycanproduceafastdVDS/dtwithhighgatebounceresultinginacombinedavalancheandFBSOAeffectwithhighnonuniformcurrentdensityflowingthroughtheparasiticbipolarRB.VGS(DUT)bounceduetoCxdV/dtIDS(DUT)6TYPE3(withmoredetail)DiodetRRtestcircuitusingacontrolledamountofunclampedinductanceIASLGATEVDDLLOADVDSIDSRGDUTVGSLDInthismode,theMOSFETentersavalancheduringadiodereverserecoveryevent.TheresultingMOSFETdraincurrentequalsthediodereverserecoveryplustheavalanchecurrent.DioderecoverycanproduceafastdVDS/dtwithhighgatebounceresultinginacombinedavalancheandFBSOA(linearmodeoperationwithVDSBVDSS)effectwiththepotentialforhighcurrentdensityflowingthroughthedistributedparasiticbipolarRB.ThistypeofeventcanoccurforsynchronousrectifiersandcanproducealotofstressontheMOSFET.VDS(DUT)tAVVGS(DUT)bounceduetoCGDxdVDS/dtVFISD(DUT)QRRNote:forconvenienceISDisplotted(notIDS)asdiodeQRRisoftendepictedusingthistypeofcurrentwaveform.7DC-DCPackageTechnologiesPQFN&MLPPQFN&MLP(Thermalenhanced)(Thermalenhanced)8X88X8SOSO--8/TSSOP8/TSSOP--8/SSOT8/SSOT--66DrainSourceBondWiresDrMOS(MCM)DrMOS(MCM)5X6dual5X6dualCSPCSPSourceMetalGateBondWireSourceBondWiresDrainTOTO--252(D252(D--PAK)PAK)5mmX6mm(Power565mmX6mm(Power56TMTM))1.0x1.52x52x56x66x63x23x23x2dual3x33x3(Power33(Power33TMTM))3x2dualSOSO--88TSSOPTSSOP--88SSOTSSOT--668PackageResistancevs.SourceInductance0.00.51.01.52.02.53.03.50.00.51.01.52.02.53.0SourceInductance(nH)PackageResistance(mΩ)Power33Power56D-PAKSO-82x2MLPNote:Power56&339ThermalResistance(RΘJAvs.RΘJC)4550556065051015202530MaximumRatedThermalResistance[Junction-to-Case]RΘJC(°C/W)MaximumRatedThermalResistance[Junction-to-Ambient]-RΘJA(°C/W)Power33Power56D-PAKSO-82x2MLPNote:PCBuses2oz.copperwith1in2mountingarea10MOSFETActiveCellCross-SectionN-EpiN+SubstrateDrainMetalSOURCEMETALGateN+SourceChannelCGDCDSCGSPtypeBodydielectricRCHANNELREPIRSUBSTRATEP+contactDRAINCDSCGSCGDSOURCERGGATE2D–CrossSection11MOSFETDieinPQFN5x6(Optional)SOURCEGATEDiepackagedinPQFN5x6CDSCGSCGDDRAINRGSOURCEGATERSLSLGNote:LDandRDcontributionfromPower56isverylowduetodirectdieattachtocopperheaderandareomittedforthisexample.LGRG(bond)Note:RGcontributionfrombondwireistypicallymuchlowerthansiliconRGandcanoftencanbeignored.RSLS12TrenchMOSFETTechnologiesN+SourceShieldPBodyN-EpiNtypeSubstrateDRAINSOURCEGateGateN-EpiNtypeSubstrateDRAINSOURCEN-EpiNtypeSubstrateDRAINSOURCEN+SourcePBodyN+SourcePBodyThickoxideforlowCGDOxideGateP+contactStandardTrenchTrenchwiththickbottomoxide(TBO)ShieldedGate13SyncFETTMN-EpiN+SubstrateSOURCEMETALN+SourceChannelPtypeBodydielectricP+contactGateSchottkycontactSourceN-EpiDrainSourceGateCDSSchottkydiodeactivecellDrainMetalMOSFETactivecellCGDRGN+SubstrateDrainMetalCGSSyncFETTMadvantages•Lowerforwardconductiondrop(VF)andlowerreverserecovercharge(QRR).•Softerdioderecovery(tB/tA)14SynchronousBuckWaveformsLFCFRLOADVINControllerandDriverQ1Q2VOUT=DxVINIINDUCTORt0PWMVGS(Q1)VGS(Q1)VGS(Q2)VDS(Q1)VDS(Q2)IDS(Q1)IDS(Q2)t1t2t3t4t6t515ControlMOSFET(Q1)LG(HS_pkg)RG(HS)LF(OUT)CF(OUT)RLOADSynchronousMOSFET(Q2)RDRV(HS)LG(LS)RG(LS)RDRV(LS)CSNUBRSNUBSynchronousBuckSchematicwithCircuitInductanceLG(