上海沪生电子产品使用说明书

WWW.HUSOON.COM•CompatiblewithMCS-51®Products8KBytesofIn-SystemProgrammable(ISP)FlashMemory–Endurance:1000Write/EraseCycles4.0Vto5.5VOperatingRangeFullyStaticOperation:0Hzto33MHzThree-levelProgramMemoryLock256x8-bitInternalRAM32ProgrammableI/OLinesThree16-bitTimer/CountersEightInterruptSourcesFullDuplexUARTSerialChannelLow-powerIdleandPower-downModesInterruptRecoveryfromPower-downModeWatchdogTimerDualDataPointerPower-offFlagDescriptionTheAT89S52isalow-power,high-performanceCMOS8-bitmicrocontrollerwith8Kbytesofin-systemprogrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindus-try-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememorypro-grammer.Bycombiningaversatile8-bitCPUwithin-systemprogrammableFlashonamonolithicchip,theAtmelAT89S52isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89S52providesthefollowingstandardfeatures:8KbytesofFlash,256bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextinterruptorhardwarereset.Rev.1919A-07/018-bitMicrocontrollerwith8KBytesIn-SystemProgrammableFlashAT89S52AT89S522TQFP1234567891011333231302928272625242344434241403938373635341213141516171819202122(MOSI)P1.5(MISO)P1.6(SCK)P1.7RST(RXD)P3.0NC(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4(T1)P3.5P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPNCALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P1.4P1.3P1.2P1.1(T2EX)P1.0(T2)NCVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)(WR)P3.6(RD)P3.7XTAL2XTAL1GNDGND(A8)P2.0(A9)P2.1(A10)P2.2(A11)P2.3(A12)P2.4PLCC78910111213141516173938373635343332313029(MOSI)P1.5(MISO)P1.6(SCK)P1.7RST(RXD)P3.0NC(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4(T1)P3.5P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPNCALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)65432144434241401819202122232425262728(WR)P3.6(RD)P3.7XTAL2XTAL1GNDNC(A8)P2.0(A9)P2.1(A10)P2.2(A11)P2.3(A12)P2.4P1.4P1.3P1.2P1.1(T2EX)P1.0(T2)NCVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)PinConfigurationsPDIP12345678910111213141516171819204039383736353433323130292827262524232221(T2)P1.0(T2EX)P1.1P1.2P1.3P1.4(MOSI)P1.5(MISO)P1.6(SCK)P1.7RST(RXD)P3.0(TXD)P3.1(INT0)P3.2(INT1)P3.3(T0)P3.4(T1)P3.5(WR)P3.6(RD)P3.7XTAL2XTAL1GNDVCCP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)AT89S523BlockDiagramPORT2DRIVERSPORT2LATCHP2.0-P2.7FLASHPORT0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDUALDPTRINSTRUCTIONREGISTERBREGISTERINTERRUPT,SERIALPORT,ANDTIMERBLOCKSSTACKPOINTERACCTMP2TMP1ALUPSWTIMINGANDCONTROLPORT1DRIVERSP1.0-P1.7PORT3LATCHPORT3DRIVERSP3.0-P3.7OSCGNDVCCPSENALE/PROGEA/VPPRSTRAMADDR.REGISTERPORT0DRIVERSP0.0-P0.7PORT1LATCHWATCHDOGISPPORTPROGRAMLOGICAT89S524PinDescriptionVCCSupplyvoltage.GNDGround.Port0Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogram-mingandoutputsthecodebytesduringprogramverifica-tion.Externalpullupsarerequiredduringprogramverification.Port1Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollowingtable.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Port2Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpul-lupswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2