第二章CMOS制备基本流程

2.1CMOS制造工艺流程简介•WewilldescribeamodernCMOSprocessflow.•Processdescribedhererequires16masksand100processsteps.1第二章CMOS制备基本流程StagesofICFabrication2•InthesimplestCMOStechnologies,weneedtorealizesimplyNMOSandPMOStransistorsforcircuitslikethoseillustratedbelow.CMOSDigitalGates反相电路或非门：同时输入低电平时才能获得高电平输出3PMOSandNMOSwafercrosssectionafterfabrication2-LevelMetalCMOS两层互连布线的CMOS4•有源器件（MOS、BJT等类似器件），必须在外加适当的偏置电压情况下，器件才能正常工作。•对于MOS管，有源区分为源区和漏区，在进行互联之前，两者没有差别。••••••••ChoosingaSubstrateActiveRegionNandPWellGateTiporExtensionSourceandDrainContactandLocalInterconnectMultilevelMetalizationProcessingPhases51µmPhotoresist40nmSiO2Choosethesubstrate(type,orientation,resistivity,wafersize)•Initialprocessing:-Wafercleaning-thermaloxidation,H2O(≈40nm,15min.@900ºC)-nitrideLPCVD(低压化学气相沉积)(≈80nm@800ºC)•Substrateselection:-moderatelyhighresistivity(25-50ohm-cm)-(100)orientation-P-type.80nmSi3N4ChoosingaSubstrateSi,(100),PType,25~50Ωcm1stMaskPhotoresist•spinningandbaking@100ºC(≈0.5-1.0µm)62.2有源区的形成•Photolithography-Mask#1patternalignmentandUVexposure-Rinseawaynon-patternPR-DryetchtheNitridelayer--PlasmaetchwithFluorineCF4orNF4Plasma-StripPhotoresist(H2SO4或O2plasma)ActiveAreaDefinition(主动区)SiO2Si3N4Photoresist7•WetOxide(thickSiO2)-H2O(≈500nm,90min.@1000ºC)•StripNitridelayer-Phosophoricacid(磷酸)orplasmaetch，选择性问题FieldOxideGrowth-LOCOS:LocalOxidationofSilicon(局部硅氧化工艺)SiO2Si3N4•薄的SiO2层，厚的Si3N4层，避免鸟喙(bird’sbeak)的影响8•场区:很厚的氧化层，位于芯片上不做晶体管、电极接触的区域，可以起到隔离晶体管的作用。•Photolithography(套刻)-Mask#2patternalignmentandUVexposure•IonImplantation离子注入-B+ionbombardment-PenetratethinSiO2andfieldSiO2--反型：半导体表面的少数载流子浓度等于体内的多数载流子浓度时，半导体表面开始反型。-150-200keVfor1013cm-2--ImplantationEnergyandtotaldoseadjustedfordepthandconcentrationP-wellFabrication•StripPhotoresist-Rinseawaynon-patternPR2.3N阱和P阱的形成SiO2Photoresist9•IonImplantation-P+ionbombardment-PenetratethinSiO2andfieldSiO2-300-400keVfor1013cm-2--ImplantationEnergyandtotaldoseadjustedfordepthandconcentration•StripPhotoresistN-wellFabrication•Photolithography-Mask#3patternalignmentandUVexposure-Rinseawaynon-patternPR10•ThermalAnneal(热退火)-Repaircrystallatticestructuredamageduetoimplantation•DryFurnace(N2ambient，防止氧化层生成)-Anneal30min@800˚CorRTA(快速热退火)10sec@1000˚C-Drive-in4-6hours@1000˚C-1100˚CThermalAnnealandDiffusion•NandPDrive-in(扩散推进)-Thermaldiffusionofdopanttoshallowerthandesireddepth--Drive-inisacumulativeprocess!11•Photolithography-Mask#4patternalignmentandUVexposure-Rinseawaynon-patternPR-B+ionbombardment-50-75keVfor1-5×1012cm-2--ImplantationEnergyandtotaldoseadjustedfordepthandconcentration•StripPhotoresistThresholdAdjustment,P-typeNMOS•IonImplantation2.4栅电极的制备开启电压调整12调整之前P阱的掺杂浓度调整时的注入剂量ThresholdAdjustment,N-typePMOS•Photolithography-Mask#5patternalignmentandUVexposure-Rinseawaynon-patternPR-As+ionbombardment-75-100keVfor1-5×1012cm-2--ImplantationEnergyandtotaldoseadjustedfordepthandconcentration•StripPhotoresist•IonImplantation13•Removeexistinggateregionoxide•FurnaceSteps-ThermalAnneal-Oxidegrowth3-5nm--O2ambient--0.5-1hour@800°CGateOxideGrowth栅极氧化层生长-HFetch，具有良好的选择性--DryFurnace(N2ambient)--30min@800˚C14•LPCVDDepositionofSi-Silane硅烷•Amorphousorpolycrystallinesiliconlayerresults•IonImplantation-P+orAs+(N+)implantdopesthepoly(typically5×1015cm-2)PolysiliconGateDeposition•0.3-0.5umSiO2多晶硅薄膜15热分解•Photolithography-Mask#6patternalignmentandUVexposure•PlasmaEtch-Anisotropicetch各向异性蚀刻--Verticaletchratehigh--LateraletchratelowGatePatterning（栅极的图形化）-Rinseawaynon-patternPR•Clorine(氯)orBromine(溴)basedforSiO2selectivity16目标：•NMOS器件中的N-注入区•PMOS器件中的P-注入区•多晶硅栅的两侧形成侧壁隔离层的薄氧化层2.5前端或延伸区(LDD)的形成17LDD:•LightlyDopedDrain(轻掺杂漏)•Reduceshortchanneleffectsduetogatevoltagemagnitudesandelectricfields•SourceandDrainmustbelayeredasNMOS:N+N-PorPMOS:P+P-NExtension(LDD)FormationNMOS•Photolithography-Mask#7patternalignmentandUVexposure-Rinseawaynon-patternPR-P+ionbombardment-50keVfor5×1013cm-2•StripPhotoresist•IonImplantation18•Photolithography•Mask#8patternalignmentandUVexposure•Rinseawaynon-patternPR•IonImplantation•B+ionbombardment•50keVfor5×1013cm-2•StripPhotoresistExtension(LDD)FormationPMOS19SiO2隔离介质层•CVDorLPCVDDepositionofSiO2•SilaneandOxygenOr•0.5um•Providesspacingbetweengateandsource-drain.SiO2SpacerDeposition20•Photolithography•Mask#6oversizedpatternalignmentandUVexposure•Rinseawaynon-patternPR•Verticaletchratehigh•Lateraletchratelow•StripPhotoresistAnisotropicSpacerEtch•PlasmaEtch•Anisotropicetch•Flourinebased21•ScreenOxideGrowth•ThinSiO2layer~10nmtoscattertheimplantedions•Photolithography•Mask#9patternalignmentandUVexposure•Rinseawaynon-patternPR•IonImplantation•As+ionbombardment•75keVfor2-4×1015cm-2•StripPhotoresistNMOSSourceandDrainImplant2.6源漏区的形成Arsenic•Reducechanneling22•Photolithography•Mask#10patternalignmentandUVexposure•Rinseawaynon-patternPR•IonImplantation•B+ionbombardment•5-10keVfor1-3×1015cm-2•StripPhotoresistPMOSSourceandDrainImplant23•N+andP+Drive-in•Thermaldiffusionofdopanttoshallowerthandesireddepth•Drive-inisacumulativeprocess!•DryFurnace(N2ambient)•Anneal30min@900˚CorRTA60sec@1000˚C-1050˚CTransientEnhancedDiffusion(