哈工大CPU设计代码

五.详细代码1CPU例化libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.libraryUNISIM;--useUNISIM.VComponents.all;entityCPUisport(CLK:instd_logic;RST:instd_logic;DBUS:inoutstd_logic_vector(15downto0);ABUS:outstd_logic_vector(15downto0);nMREQ:outstd_logic;--片选nRD:outstd_logic;--读信号nWR:outstd_logic;--写信号nBHE:outstd_logic;--高位访问允许nBLE:outstd_logic;--低位访问允许abus_data:outstd_logic_vector(15downto0);dbus_data:outstd_logic_vector(15downto0);cs_data:outstd_logic;wr_data:outstd_logic;rd_data:outstd_logic;bh_data:outstd_logic;bl_data:outstd_logic;beat:outstd_logic_vector(3downto0);ir:outstd_logic_vector(15downto0);cy_out:outstd_logic;z_out:outstd_logic);endCPU;architectureBehavioralofCPUiscomponentjiepaiisPort(clk:inSTD_LOGIC;rst:inSTD_LOGIC;k:outSTD_LOGIC_VECTOR(3downto0));endcomponent;componentquzhiisPort(rst:instd_logic;--复位k0,k1:instd_logic;--时钟控制pc_in_flag:instd_logic;--PC回写允许ir_in:instd_logic_vector(15downto0);--IR进入pc_in:instd_logic_vector(15downto0);--PC回写visit_mem_flag:outstd_logic;--访存信号pc_out:outstd_logic_vector(15downto0);--PC输出ir_out:outstd_logic_vector(15downto0)--IR输出);endcomponent;componentyunsuanisPort(rst:instd_logic;--复位信号k0,k1,k2,k3:instd_logic;--节拍控制rewrite_flag:instd_logic;--寄存器回写允许rewrite_data:instd_logic_vector(7downto0);--寄存器回写数据ir_in:instd_logic_vector(15downto0);--指令IR进入aluout:inoutstd_logic_vector(7downto0);--运算结果输出addr:outstd_logic_vector(15downto0);--准备好的地址输出if_reg:outstd_logic;--是否回写寄存器if_pc:outstd_logic;--是否回写pcm_r:outstd_logic;--给存储器管理模块读信号m_w:outstd_logic;--给存储器管理模块写信号CyFlag:outstd_logic;ZFlag:outstd_logic;toHX:outstd_logic_vector(15downto0));endcomponent;componentcunchuisPort(rst:instd_logic;--复位信号m_w_in:inoutstd_logic;--写请求m_r_in:inoutstd_logic;--读请求c_w_out:outstd_logic;c_r_out:outstd_logic;k2:instd_logic;--节拍控制aluout_in:instd_logic_vector(7downto0);--Aluout输入dataFromMem:instd_logic_vector(7downto0);dataToMem:outstd_logic_vector(7downto0);outToHX:outstd_logic_vector(7downto0)--输出到回写模块);endcomponent;componentfangcunisPort(k0,k1,k2:instd_logic;--节拍控制qz_visit_flag:instd_logic;--取址模块取址信号c_r_in:instd_logic;c_w_in:instd_logic;pc_in:instd_logic_vector(15downto0);--pc输入addr_in:instd_logic_vector(15downto0);data_in:instd_logic_vector(7downto0);--存数的时候用DBUS:inoutstd_logic_vector(15downto0);ABUS:outstd_logic_vector(15downto0);nMREQ:outstd_logic;--片选nRD:outstd_logic;--读信号nWR:outstd_logic;--写信号nBHE:outstd_logic;--高位访问允许nBLE:outstd_logic;--低位访问允许data_out:outstd_logic_vector(7downto0);--取得数据输出ir_out:outstd_logic_vector(15downto0)--取得指令输出);endcomponent;componenthuixieisPort(k3:instd_logic;if_pc_in:instd_logic;if_reg_in:instd_logic;from_M:instd_logic_vector(7downto0);pc_in:instd_logic_vector(15downto0);--用于处理jz,jcjmp_in:instd_logic_vector(15downto0);ir_in:instd_logic_vector(15downto0);pc_update:outstd_logic;--PC回写标志reg_update:outstd_logic;--Reg回写标志pcnew:outstd_logic_vector(15downto0);Rdata:outstd_logic_vector(7downto0));endcomponent;--信号赋值signalk0_cpu,k1_cpu,k2_cpu,k3_cpu:std_logic;signalrepc_flag_cpu:std_logic;signalirToqz_cpu:std_logic_vector(15downto0);signalrepc_cpu:std_logic_vector(15downto0);signalqzVmem_flag_cpu:std_logic;signalpcOut_cpu:std_logic_vector(15downto0);signaltoHX_cpu:std_logic_vector(15downto0);signalirOut_cpu:std_logic_vector(15downto0);signalrereg_flag_cpu:std_logic;signalrereg_data_cpu:std_logic_vector(7downto0);signalaluout_cpu:std_logic_vector(7downto0);signaladdr_cpu:std_logic_vector(15downto0);signalif_reg_cpu:std_logic;signalif_pc_cpu:std_logic;signalm_r_cpu:std_logic;signalm_w_cpu:std_logic;signalc_r_cpu:std_logic;signalc_w_cpu:std_logic;signaldataFromMem_cpu:std_logic_vector(7downto0);signaldataToMem_cpu:std_logic_vector(7downto0);signaloutToHX_cpu:std_logic_vector(7downto0);signalabus_cpu:std_logic_vector(15downto0);signaldbus_cpu:std_logic_vector(15downto0);signalcs_data_cpu:std_logic;signalwr_data_cpu:std_logic;signalrd_data_cpu:std_logic;signalbh_data_cpu:std_logic;signalbl_data_cpu:std_logic;beginu1:jiepaiportmap(clk=CLK,rst=RST,k(0)=k0_cpu,k(1)=k1_cpu,k(2)=k2_cpu,k(3)=k3_cpu);u2:quzhiportmap(rst=RST,k0=k0_cpu,k1=k1_cpu,pc_in_flag=repc_flag_cpu,ir_in=irToqz_cpu,pc_in=repc_cpu,visit_mem_flag=qzVmem_flag_cpu,pc_out=pcOut_cpu,ir_out=irOut_cpu);u3:yunsuanportmap(rst=RST,k0=k0_cpu,k1=k1_cpu,k2=k2_cpu,k3=k3_cpu,rewrite_flag=rereg_flag_cpu,rewrite_data=rereg_data_cpu,ir_in=irOut_cpu,aluout=aluout_cpu,addr=addr_cpu,if_reg=if_reg_cpu,if_pc=if_pc_cpu,m_r=m_r_cpu,m_w=m_w_cpu,CyFlag=Cy_out,ZFlag=Z_out,toHX=toHX_cpu);u4:cunchuportmap(rst=RST,m_w_in=m_w_cpu,m_r_in=m_r_cpu,c_w_out=c_w_cpu,c_r_out=c_r_cpu,k2=k2_cpu,aluout_in=aluout_cpu,dataFromMem=dataFromMem_cpu,dataToMem=dataToMem_cpu,outToHX=outToHX_cpu);u5:fangcunportmap(k0=k0_cpu,k1=k1_cpu,k2=k2_cpu,qz_visit_flag=qzVmem_flag_cpu,c_r_in=c_r_cpu,c_w_in=c_w_cpu,pc_in=pcOut_cpu,addr_in=addr_cpu,data_in=dataToMem_cpu,DBUS=DBUS,ABUS=abus_cpu,nMREQ=cs_