基于FPGA的温度传感器DS18B20读写代码

温度传感器DS18B20Verilog读写代码`timescale1ns/1psmoduleDS18B20(clk,clk1m,dq,rst_n,reset_n,DS_dataout,DS_fifo_wr);//约5-6ms完成一次读温度inputclk;//50M主时钟inputclk1m;inoutdq;//单数据总线inputrst_n;//复位inputreset_n;output[23:0]DS_dataout;//接收数据寄存器，保存直至下一个数据来到outputDS_fifo_wr;//写数据到FIFO，产生一个时钟周期的高电平regdq;reg[15:0]DS_dataout_r;regDS_wr_int;//FIFO写入请求的下降沿信号//------------------------------------------定义的状态parameter[3:0]RESET=0;//复位状态parameter[3:0]CMD_CC=1;//跳过ROM，忽略64位ROM地址parameter[3:0]WRITE_BYTE=2;parameter[3:0]WRITE_LOW=3;parameter[3:0]WRITE_HIGH=4;parameter[3:0]READ_BIT=5;parameter[3:0]CMD_44=6;parameter[3:0]CMD_BE=7;//parameter[3:0]WAIT800MS=8;parameter[3:0]GET_TMP=9;parameter[3:0]WAIT4MS=10;reg[3:0]STATE;reg[7:0]write_temp;reg[15:0]TMP;regtmp_bit;reg[3:0]WRITE_BYTE_CNT;reg[1:0]WRITE_LOW_CNT;reg[1:0]WRITE_HIGH_CNT;reg[1:0]READ_BIT_CNT;reg[3:0]GET_TMP_CNT;reg[16:0]cnt;regtemp;reg[2:0]WRITE_BYTE_FLAG;always@(posedgeclk1mornegedgereset_n)begin:STATE_TRANSITIONif(reset_n==1'b0)beginSTATE=RESET;write_temp=8'b00000000;WRITE_BYTE_CNT=0;WRITE_LOW_CNT=0;WRITE_HIGH_CNT=0;READ_BIT_CNT=0;GET_TMP_CNT=0;cnt=17'd0;WRITE_BYTE_FLAG=0;TMP=0;DS_wr_int=1'b1;endelsebegincase(STATE)RESET:beginif(cnt=17'd0&cnt17'd500)begindq=1'b0;cnt=cnt+1'b1;STATE=RESET;endelseif(cnt=17'd500&cnt17'd510)begindq=1'bz;cnt=cnt+1'b1;STATE=RESET;endelseif(cnt=17'd510&cnt17'd750)begintemp=dq;if(cnt==17'd580)begintemp=dq;endcnt=cnt+1'b1;STATE=RESET;endelseif(cnt=17'd750)begincnt=17'd0;STATE=CMD_CC;endendCMD_CC:beginwrite_temp=8'b11001100;STATE=WRITE_BYTE;endWRITE_BYTE:begincase(WRITE_BYTE_CNT)0,1,2,3,4,5,6,7:beginif((write_temp[WRITE_BYTE_CNT])==1'b0)beginSTATE=WRITE_LOW;endelsebeginSTATE=WRITE_HIGH;endWRITE_BYTE_CNT=WRITE_BYTE_CNT+1'b1;end8:beginif(WRITE_BYTE_FLAG==0)beginSTATE=CMD_44;WRITE_BYTE_FLAG=1;endelseif(WRITE_BYTE_FLAG==1)beginSTATE=RESET;WRITE_BYTE_FLAG=2;endelseif(WRITE_BYTE_FLAG==2)beginSTATE=CMD_BE;WRITE_BYTE_FLAG=3;endelseif(WRITE_BYTE_FLAG==3)beginSTATE=GET_TMP;WRITE_BYTE_FLAG=0;endWRITE_BYTE_CNT=0;enddefault:beginSTATE=RESET;endendcaseendWRITE_LOW:begincase(WRITE_LOW_CNT)0:begindq=1'b0;if(cnt==17'd70)begincnt=17'd0;WRITE_LOW_CNT=1;endelsebegincnt=cnt+1'b1;endend1:begindq=1'bz;if(cnt==17'd5)begincnt=17'd0;WRITE_LOW_CNT=2;endelsebegincnt=cnt+1'b1;endend2:beginSTATE=WRITE_BYTE;WRITE_LOW_CNT=0;enddefault:beginWRITE_LOW_CNT=0;endendcaseendWRITE_HIGH:begincase(WRITE_HIGH_CNT)0:begindq=1'b0;if(cnt==17'd8)begincnt=17'd0;WRITE_HIGH_CNT=1;endelsebegincnt=cnt+1'b1;endend1:begindq=1'bz;if(cnt==17'd72)begincnt=17'd0;WRITE_HIGH_CNT=2;endelsebegincnt=cnt+1'b1;endend2:beginSTATE=WRITE_BYTE;WRITE_HIGH_CNT=0;enddefault:beginWRITE_HIGH_CNT=0;endendcaseendCMD_44:beginwrite_temp=8'b01000100;STATE=WRITE_BYTE;endCMD_BE:beginwrite_temp=8'b10111110;STATE=WRITE_BYTE;endREAD_BIT:begincase(READ_BIT_CNT)0:begindq=1'b0;if(cnt==17'd4)beginREAD_BIT_CNT=1;cnt=17'd0;endelsebegincnt=cnt+1'b1;endend1:begindq=1'bz;if(cnt==17'd4)beginREAD_BIT_CNT=2;cnt=17'd0;endelsebegincnt=cnt+1'b1;endend2:begindq=1'bz;tmp_bit=dq;if(cnt==17'd1)beginREAD_BIT_CNT=3;cnt=17'd0;endelsebegincnt=cnt+1'b1;endend3:begindq=1'bz;if(cnt==17'd55)begincnt=17'd0;READ_BIT_CNT=0;STATE=GET_TMP;endelsebegincnt=cnt+1'b1;endenddefault:beginREAD_BIT_CNT=0;endendcaseendGET_TMP:begincase(GET_TMP_CNT)0:beginSTATE=READ_BIT;GET_TMP_CNT=GET_TMP_CNT+1'b1;end1,2,3,4,5,6,7,8,9,10,11,12:beginSTATE=READ_BIT;TMP[GET_TMP_CNT-1]=tmp_bit;GET_TMP_CNT=GET_TMP_CNT+1'b1;end13:beginGET_TMP_CNT=0;STATE=WAIT4MS;DS_dataout_r=TMP;endendcaseendWAIT4MS:beginSTATE=WAIT4MS;DS_wr_int=1'b0;enddefault:beginSTATE=RESET;endendcaseendendassignDS_dataout=DS_dataout_r;regDS_rx_int0,DS_rx_int1,DS_rx_int2;//DS_wr_int信号寄存器，捕捉下降沿滤波用always@(posedgeclkornegedgerst_n)beginif(!rst_n)beginDS_rx_int0=1'b0;DS_rx_int1=1'b0;DS_rx_int2=1'b0;endelsebeginDS_rx_int0=DS_wr_int;DS_rx_int1=DS_rx_int0;DS_rx_int2=DS_rx_int1;endendassignDS_fifo_wr=~DS_rx_int1&DS_rx_int2;//捕捉到下降沿后，DS_fifo_wr拉高保持一个主时钟周期endmodule