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当前位置:首页 > 电子/通信 > 电子设计/PCB > 李波-多层板ICD缺陷DOE实验分析
©ViasystemsKalex20091DOEreportforimprovingICDforA121626Preparedby:PDE–李波Nov04th,09©ViasystemsKalex20092CustomscomplainedICDforA121216.X-Sectionpicturesasbelow.D/C:2809.Defectholesizeisonly3.35mm,Thereisn’tthedefectinotherholesize.Onlytwopcswerefoundhavingthisdefect.Background©ViasystemsKalex20093WecheckedourinventoryafterwereceivedthiscomplaintfromcustomerandfoundtherearesameD/Cinourstore.D/C:2809:148pcsD/C:2509:52pcsD/C:2609:6pcsWeselect6pcsfromabove3D/C(2pcsforeachD/C)andperformCross-sectionatthedesignatedlocation,pleaserefertothesamplelocationbelow.(samplingmethodisrouting,andperformthermalshocktestontheboardsonetimewith288℃,10S,thanperformX-section)Finding:WedidnotfoundoutthesamedefectontheboardsfromourinventoryDefectanalysisCross-sectionwhichperformedbyinternalLab©ViasystemsKalex20094DOEprojectforthedefectFactorLow(-1)High(+1)Standard3303Swellertime7'309'007'30Permanganatetime12'0015'0012'00PlasmaprocessNOYESNOPTHtimestwiceoncetwicePlatingcopperthicknessinholewall2.0mil1.0mil1.0milDiptimeincatalystbath12'006'006'00FactorsandlevelsforDOEplan©ViasystemsKalex20095RunOrderswellertimepermanganatetimeplasmaprocessdiptimeincatalystbathPTHtimesplatingcopperthicknessinholewallQtyofsample1++-+++22+--+++23-+-+++24---+++25--++++26----++27---+-+28+--++-2Sample16pnlsforDOEevaluation:DOEprojectforthedefect©ViasystemsKalex20096Testvehicle:A121626withIT180materialwasselected.Testflow:Inner→Drilling→PTH→panelplating→OuterDryFilm→PatternPlating→Etching→WetFilmTestplan©ViasystemsKalex20097Testitemsforsamplepanels:1.Desmearratetestwhenperformingsamplepanels;2.SEManalysisafterdesmearforsamplepanels;3.ThermalshocktestafterW/Fwithconditionof288℃,10Sec,1times(requiredconditionbycustomer)andtheconditionof288℃,10Sec,5times;4.EDXanalysisfordefectholes.Testplan©ViasystemsKalex20098DesmearratetestresultRunorderDesmearrate(mg/dm2)requirement(mg/dm2)138.220~40236.920~40332.620~40429.320~40534.520~40630.220~40729.820~40830.620~40TestResultandAnalysis©ViasystemsKalex20099NO.FibreResinInnerlayer12TestResultandAnalysis©ViasystemsKalex200910NO.FibreResinInnerlayer34TestResultandAnalysis©ViasystemsKalex200911NO.FibreResinInnerlayer56TestResultandAnalysis©ViasystemsKalex200912TestResultandAnalysisNO.FibreResinInnerlayer78©ViasystemsKalex200913SEM切片分析:SEManalysisTestResultandAnalysis1.Thereisnosmearinfibreforallsamples;2.Thereisnosmearoninnerlayerforallsamples;3.Comparingalltheconstructionofresin,Thesampleofrunorder2hasbetterdesmeartexturethanothersontheresin;4.Theconditionofrunorder2istoincreasetheswellereffect.5.AfterdiscussingwithR&H,weplantoincreasethetemperatureofswellersolutionfrom78℃to80℃forthisP/Ntoimprovetheswellereffect.©ViasystemsKalex200914Thermalshocktestresult3.35mmholeswithtwointerconnectiontohoewall3.35mmholeswithteninterconnectiontohoewall1.2mmholes0.5mmholes1NONONONONO0.98milNO2NONONONONO1.38milNO3NONONONONO0.98milNO4NONONONONO1.77milNO5NONONONONO1.97milNO6NONONONONO1.38milNO7NONONONONO0.49milNO8NONONONONO1.18milNOrunorder288℃,10sec,1timesConditionoftesttestresultICDsmearoninnerlayercopperwicking(requirement≤3mil)PullawayTestResultandAnalysis©ViasystemsKalex2009153.35mmholeswithtwointerconnectiontoholewall3.35mmholeswithteninterconnectiontoholewall1.2mmholes0.5mmholes1NOYESNONONO0.98milNO2NOYESNONONO1.38milNO3NOYESNONONO0.98milNO288OC,10sec,5timesrunordertestconditionSmearoninnerlayercopperwicking(requirement≤3.0mil)TestresultICDPullawayTestResultandAnalysisThermalshocktestresult©ViasystemsKalex200916TestResultandAnalysis3.35mmholeswithtwointerconnectiontoholewall3.35mmholeswithteninterconnectiontoholewall1.2mmholes0.5mmholes4NOYESNONONO1.77milNO5NOYESNONONO1.97milNO6NOYESNONONO1.38milNOrunorder288OC,10sec,5timesICDsmearoninnerlayercopperwicking(requirement≤3mil)testconditionTsetresultPullawayThermalshocktestresult©ViasystemsKalex200917TestResultandAnalysis3.35mmholeswithtwointerconnectiontoholewall3.35mmholeswithteninerconnectiontoholewall1.2mm0.5mm7NOYESNONONO0.49milNO8NOYESNONONO1.47milNO288OC,10sec,5timestestconditionrunorderTsetresultsmearoninnerlayercopperICDwicking(requirement≤3mil)PullawayThermalshocktestresult©ViasystemsKalex200918EDXresultTestResultandAnalysis©ViasystemsKalex2009191.Thermalshockintheconditionof288℃,10Sec,1timebycustom’srequirement,ThereisnoICDforallsamplepanels.2.Thermalshockintheconditionof288,10Sec,5times,ICDwerefoundonlyfor3.35mmholewithtwointerconnectiontoholewall,thereisnoICDfoundfor3.35mmholeswithteninterconnectiontoholewallandotherholes.3.ThereisnoBrfoundoninnerlayercopperintheEDXtest,Thisprovedthatthereisnosmearoninnerlayercopper.4.SoICDforA121626isnotaffectedbysmearontheinnerlayercopper,theamountofinterconnectiontoholewallisthekeyfactorforthedefect.AnalysisforthermalshockresultandEDXresultTestResultandAnalysis©ViasystemsKalex200920TestResultandAnalysisX-sectionof3.35mmholeswithtwointerconnectiontoholewallafterthermalshockwiththeconditionof288℃,10S,5times©ViasystemsKalex200921X-sectionof3.35mmholeswithteninterconnectiontoholewallandotherholesafterthermalshockwiththeconditionof288℃,10S,5tim
本文标题:李波-多层板ICD缺陷DOE实验分析
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