DDR1-2-3-SDRAM功能对比

DDR1/2/3/SDRAM&FunctionalityintroductionDRAMproductapplicationdepart.WinbondElectronicsCorp.•DDR1/2/3/SDRAMFunctionalitycompare•DifferentialfunctionintroduceAgenda:FeaturesItemDDR-IIDDR-IAdvantageofDDR-IITransferRate533/667/800Mbps266/333/400MbpsPre-fetch4-bits2-bitsBurstLength4/82/4/8CoreVoltage1.8V2.5VI/OInterfaceSSTL_18SSTL_2PackageBGATSOPII/FBGAHighspeedPowerreductionDLLEssentialEssentialDatastrobe(DQS)Single/DifferentialSingleOCDcontrolODTcontrolN/ANosupported50/75/150ohmCLKDifferentialDifferentialCASLatency3-72/2.5/3AdditionLatency0/1/2/3/4NosupportedWriteLatencyReadLatency–1tCK1tCKNewfunctionsrealizehighbusutilizationandsignalintegrityDatarate2/tck2/tckDDR-III1066/1333/1600Mbps8-bits4(BC)/8EssentialDifferentialDifferential5-102/tckMRS(2)setting5-80,CL-1,CL-2ZQcalibrationDQScalibrationRZQ/n,DYNAMIC1.5VSSTL_15BGASDRAMDDRRAMDDR2RAM256M256M512MtCK/MHz100-166100-200200-333Mb/s/pin100-166200-400400-667Transferrate(64bit)0.8-1.31.6-3.23.2-5.4GByte/sClockSingleDifferentialDifferentialDataStrobe(DQS)NoSingleSingle/DifferentialCASLatency2,32,2.5,33,4,5,(6)AdditiveLatency--0,1,2,3,4ReadLatency=CASLatency=CASLatency=CASLatency+ALWriteLatency01ReadLatency-1BurstLength1,2,4,8,FP2,4,84,8tAC25ns(166MHz)+/-0.7ns+/-0.5nsDLLNoYesYesVDD/V3.3(+-0.3)2.5(+-0.2)1.8(+-0.1)InterfaceLVTTL2.5VSSTL_2SSTL_18OCDcontrol-DriverstrengthDriverStrength,IO-calibration,ODTPrefetch-2n4nPackageP-TSOPII-54P-TSOPII-6660(84)pinPTFBGAICC4R,IDD4R/mA110160125SDR-DDR-DDR2Summary•DDR-IISDRAMachieveshigh-speedoperationby4-bitprefetch.•In4-bitprefetcharchitecture,DDR-IISDRAMcanread/write4timestheamountofdataasanexternalbusfrom/tomemorycellarrayforeveryclock,canbeoperated4timesfasterthantheinternalbusoperationfrequency•Externalbusclockfrequency=2timesfasterthaninternalbusoperationfrequency•Doubledatarateoutput=2timesfasterthanexternalclockfrequency4-bitPrefetch•DDR3SDRAMachieveshigh-speedoperationby8-bitsprefetch.•In8-bitprefetcharchitecture,DDR3SDRAMcanread/write8timestheamountofdataasanexternalbusfrom/tomemorycellarrayforeveryclock,canbeoperated8timesfasterthantheinternalbusoperationfrequency.•Externalbusclockfrequency=4timesfasterthaninternalbusoperationfrequency.•Doubledatarateoutput=2timesfasterthanexternalclockfrequency.DDR38-bitPrefetchDDR1,DDR2,DDR3COMPAREMemoryCoreMemoryCoreDDR2DDR1OperatingfrequencyofinternalbusI/OI/O133MHZ133MHZExternalfrequency133MHZ266MHZ266Mbps533MbpsPrefetch=2bitsPrefetch=4bitsDataBusTransferRateMemoryCoreDDR3I/O133MHZ533MHZ1066MbpsPrefetch=8bitsDDR3,DDR2&DDR1transferratecomparisonItemDDR3SDRAMDDR2SDRAMDDR1SDRAMPrefetch8-bit4-bit2-bitInternalbusoperatingfrequency100MHz100MHz100MHzExternalclockfrequency400MHz200MHz100MHzDatabusspeed800Mbps400Mbps200MbpsMax.DataRateperIO:Module(64bit):SDRPC100100MHz*1DataBits=0.1GBit/s0.8GByte/sDDRPC200100MHz*2DataBits=0.2GBit/s1.6Gbyte/sDDR2PC400200MHz*2DataBits=0.4Gbit/s3.2Gbyte/sDDR3PC800400MHZ*2DataBits=0.8Gbit/s6.4Gbyte/sDataRateSDRvs.DDRSingleDataRateDoubleDataRateDoubleDataRate210ns10ns10nsPC100PC200PC400認識DRAMcell能表現出且維持0/1狀態之最小單元1bit=1controltransistor+1capacitorBLWLC1bitDRAMcellstructureandaddressDensity–256MbitDRAMcellstructureandaddressDRAMcellstructureandaddressI/O16bitDensity–16Mx16bitBank0Bank2Bank3Bank1DRAMcellstructureandaddressDensity–4Mx4Bankx16bitI/O16bitRow(wordline)Column(bitline)RowaddressbyA0-A12ColaddressbyA0-A8DRAMcellstructureandaddress•DDR1/2/3/SDRAMFunctionalitycompare•DifferentialfunctionintroduceDDR2FunctionalblockdiagramDDRFunctionalblockdiagram•DDR2Power-UpandInitializationDDR3ResetandInitializationSequenceatPower-OnDDR3SDRAMhasemployedthe/RESETpinnewly.The/RESETpinisdrivenlowduringpower-onorinitializationprocessorwhenaresetisrequired./RESETneedstobemaintainedforminimum200μswithstablepower.DDR3ResetProcedureatPowerStableCondition(Duringoperation)/RESETneedstobemaintainedforminimum100ns.•Note1.ODT(OnDieTermination):Theterminationfunction(VTT/RTT)onDRAMchipforI/Oline.•Note2.OCD(OffChipDriver):TheStrengthcontrolfunctionofPull-up/Pull-downI/Odriver.•Note3.TAC/tDQSQandDLLMajorDifferentialfunctionintroduceNote1.ODT(OnDieTermination)InDDR-IISDRAM,themountterminationregisterconventionallymountedonthemotherboardisincorporatedinsidetheDRAMchip.TheDRAMcontrollercansettheterminationregisterforeachsignal(dataI/O,differentialdatastrobe,andwritedatamask)onandoff.•Improvedsignalintegritybycontrollingreflectednoiseonthetransferline.•Reductionofpartscostsbyreducingthepartscountsonthemotherboard.•Easiersystemdesignbyeliminatingthecomplicatedplacementandroutingfortheterminationregister.(Noimpedance,noVTTcircuit)ODTvalueshouldbedeterminedduringpower-upbyEMRSODTturnon/offiscontrolledbyODTpinNote2.OCD(Off-ChipDriver)CalibrationDDR-IISDRAMachieveshigh-speedoperationbyOCDcalibration.InOCDcalibration,theI/Odriverresistanceissettoadjustthevoltagetoequalizethepull-up/pull-downresistance.•ImprovedsignalintegritybyminimizingDQ-DQSskew.•Improvedsignalqualitybycontrollingtheovershootandundershoot.•AbsorbingprocessvariationsfromeachDRAMsupplierbyI/Odrivervoltagecalibration.•SDRw/