半导体工艺-复旦大学-蒋玉龙-Chapter-3

Chapter3CMOSProcessTechnologyOutlineI.EvolutionofSiMOSFETII.SisubstrateselectionforMOSdevicesIII.BasicstructureandadvantageofCMOSIV.FormationoftwotypesMOSFETsonthesameSisubstrateV.CMOSDeviceisolationVI.AtypicalCMOSfabricationprocessflowVII.Latch-upeffectinCMOSdevicesVIII.Sub-micronCMOSdeviceengineeringoptimizationI.WellengineeringII.ChannelengineeringIII.Source/draindopingengineeringIV.Salicide(Self-alignedsilicide)processengineeringI.EvolutionofSiMOSFET(MISFET,IGFET)‹DiscoveryofMOStransistor(1928-1960)¾IdeaofJ.Lilienfeldandhispatent:“Deviceforcontrollingelectriccurrent”(Filed-March25,1928;patentissued-march7,1933)MISFETstructureofLilienfeld:Al/Al2O3/CuSSubstrate:CuS(semiconductor)Dielectricgate:Al2O3(10-4mm)Gateelectrode:Al(100V)Electricfield:100V/10-4mm=107V/cm(ClosetothepresentSiMOSFET!)‹FirstSiMOSFETwasbuiltin1960byKahngandAttala(BellLab.)CuSSGDAl2O3Al‹1960-1970:BasicmaterialandprocessR&DdevelopedforMOStechnology¾1961MOSC-Vtechnique(byTermanandMoll)¾1962PMOS(FSC);NMOS(RCA)¾1963CMOS(F.Wanlass&C.T.Sah(萨支唐)ofFSC)¾1966The1stCMOSICswerefabricated¾SiO2/Siinterfacestudy,mobileioncontrol,…‹1970-2006rapidgrowthofMOStechnologyandindustryfromSSItoVLSI/ULSI/SoC‹MainrequirementsofMOSFETforIC¾Stableanduniformthresholdvoltage(VT)¾Largeandstabledrivingcurrent(ID)-highsurfacecarriermobility¾Lowleakage/sub-thresholdcurrent¾Largetransconductance(gm=dID/dVG)¾Highswitchingspeed/lowRCproduct¾Long-termreliability¾Lowvoltage,lowpoweroperationII.SisubstrateselectionforMOSdevices‹Waferorientation:Si(100)¾LowinterfacetrapdensityNit(111)/Nit(100)∼10¾HighersurfacecarriermobilityμS(100)μS(111)‹Dopinglevel¾ForlowerS/Dtosubstratecapacitance(CSB,CDB)→Lightdopingispreferred¾Topreventpunch-throughproblem‹WidthofthePNjunctiondepletionregionεSi—DielectricconstantofSi(11.9)ε0—Freespacepermittivity(8.85·10-14F/cm)Vbi—Built-involtage:Vbi=0.56+KT/qln(NA/ni)V—Reversebias(0)NB—SubstratedopingconcentrationIfWd≥Lg(channellength)→punch-throughThepunch-throughvoltage:VPT≈Lg2qNB/2εSiε02/10))(2(BbiSidqNVVW+=εε∴Substratedopinglevelshouldbeselectedproperlyforoptimization¾Compromise¾Usingepitaxialmaterial:p/p+¾ByionimplanttosetproperdopingprofileIII.BasicstructureandadvantageofCMOS‹CMOSinverter—basicelementofCMOSICVINMOSPMOSVOIDDVIVTNOffOn∼VDD∼0VIVDD-⏐VTP⏐OnOff∼0∼0VTNVIVDD-⏐VTP⏐Trans.Trans.Trans.≠0‹Lowpowerdissipation¾Nocurrentatstaticstate‘1’or‘0’¾DuringVI:‘1’→‘0’9PMOSTr.turnsonandprovidesalowimpedancepathtochargeCL9NMOSTr.turnsoffandhasaveryhighimpedance¾*DuringVI:‘0’→‘1’9NMOSTr.turnsonandprovidealowimpedancepathtodischargeCL9PMOSTr.turnsoffandverylittlesupplycurrentisaddedtothedischargecurrent1→0off→onon→offCLI0→10→1on→offoff→onCL1→0I∴Powerdissipationisverylow¾Only1-10%powerofNMOSgateatthesamespeedperformance¾DCPowerdissipation−leakage---negligiblesmall(∼10-9A)¾ACPowerdissipation:Charging+Dischargingcurrentofloadcapacitance(CL)P=CLVDD2fswitch*Halfoftheenergy(CLVDD2)isdissipatedintheP-ch.deviceduringcharging;*AnotherhalfisstoredinCL,laterdissipatedthroughNMOSTr.IV.FormationoftwotypesMOSFETsonthesameSisubstrate‹VariousCMOStechnology¾P-well(tub)technology–firstdevelopedCMOSprocess¾N-welltechnology—compatiblewithNMOStechnology¾Twinwelltechnology—formationN-wellandP-wellonaverylightlydopedepitaxiallayerorsubstrate‹ProblemsofsinglewellCMOSdevices¾Dopinglevelisabout10timeshigherinthewellthansubstrate→IncreaseS/DPNjunctioncapacitance→IncreasebodyeffectonVTH¾Twinwell→BetterdopingoptimizationofbothNMOSandPMOSdevices¾DopingprofileinwelliscriticaltoadjustVTHandotherdeviceparameters→WellengineeringforadvancedCMOS!‹VarietyofdifferentCMOSfabricationprocesseshasbeendevelopedandunderdevelopmentbysemiconductorcompaniesandresearch/developmentinstitutions‹Self-alignedtwinwellCMOSprocess¾Useν-Si/N+substrate*Bettercontrolofimpurityprofile*Eliminatelatch-upandbodyeffect¾Process:--ν-Siepilayergrowth--SiO2/Si3N4andwellmasklithography--N-wellimplant:P+--LocaloxidationofN-wellregion--P-wellimplant:B+--Impuritydriving-simultaneousformationofP-well&N-well--LOCOSprocessforfieldoxide--Thresholdadjustmentimplants--Gateoxideandpoly-Sigateprocess--Non-selectivep+implant(BF2)--SelectiveN+implanttoformS/DregionofN-channeldevices(As+)--Phosphorusglassdepositionandre-flow--ContactandinterconnectionprocessV.CMOSDeviceisolation‹ElectricalisolationneededbetweendevicesandhassignificanteffectonICintegrationdensityandCMOSperformance¾LocalOxidationofSilicon(LOCOS)¾ModifiedLOCOS¾Non-LOCOSisolationLocalOxidationofSilicon(LOCOS)—AverysuccessfuldeviceisolationtechnologyforbothMOSandbipolarIC‹LOCOS---Selectivethickoxidegrowthtechnique,basedonoxidationmaskingabilityofSi-nitrideSi3N4¾OxidationrateofSi3N4/Si∼1/30(ForwetoxidationwithH2Osourceat95°C)Si3N4ComsumptionduringoxidationatdifferentT高温水汽氧化气氛下氮化硅的氧化速率随温度与时间变化OXIDATIONTIME(min)‹Semi-recessedoxideisolation¾Padoxidegrowth:SiO2withcertainthicknessrequiredtoreleasestressfromSi3N4andtoavoiddislocationgenerationinSi¾CVDSi3N4depositiontoathicknessenoughtomasktheactiveregionfromoxidegrowth¾Lithographypatterntodefineactiveandfieldregions¾Si3N4etchingo