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Chapter4BasicBipolarandBiCMOSProcessTechnologyOutlineI.RequirementsandstructureofbipolardevicesforhighperformanceICII.MainfabricationprocessofoxideisolationbipolarICIII.Poly-Siself-aligned(PSA)processforbipolarVLSItechnologyIV.SBDclampsforbetterspeedperformanceofbipolarlogicIC(STTL,LSTTL,ALSTTL,SI2L….)V.Hetero-junctionbipolartransistor(HBJTorHBT)technologyVI.BiCMOStechnologyI.RequirementsandstructureofbipolardevicesforhighperformanceICMainrequirements:¾Lowjunctioncapacitance¾Lowseriesresistanceofe,b,c¾Lowbasetransittime(thinnerbase…)¾Highcurrentgain(higheremitterdoping…)¾Highbreakdownvoltage¾HighdevicedensityConventionalPNjunction-isolatedbipolarIC¾SBC(Standard-buried-collector)NPNtransistor¾Reverse-biasedPNjunctionsurroundstransistorforisolation¾Problems:(1)Consumelargerarea→Lowerdevicedensity(Theactivearea,theregionbelowemitter,onlyroughly5%oftotaldevicearea)(2)Largeparasiticcapacitance→LowerspeedHighperformanceoxideisolationbipolardevices¾Areaoccupationreduced→beneficialforhigherdensity¾Parasiticcapacitancereduced(isolation,collectorjunction,emitterjunction)→beneficialforhigherspeedIIMainfabricationprocessofoxideisolationbipolarICAnexampleofdopingengineering*StandardBuried-Collector(SBC)transistorprocess1.Substrate,buriedlayerformationandthinepitaxiallayergrowth¾Substrate:Lightlydopedp-Si;(111)/(100),doping∼1014cm-3,ρ∼10Ωcm¾Buriedlayer(subcollector):n+-Sibydiffusionorionimplantation,usinglow-diffusivityimpurities---SborAs¾Epitaxy:ND∼1015-16cm-3,ρ∼0.3-0.1Ωcm---Lightdoping→SmallerB-Cjunctionparasiticcapacitance---Toolight:(1)→Auto-dopingproblemduringgrowth(2)→Basepush-outeffect(basewideningeffect)orKirkeffect(Higher-levelelectroninjection→electronsaddtothespacechargeintheB-Cjunctionspace-chargeregion→wideningofthequasi-neutralbaselayer+wideningofB-Cspace-chargelayerintothecollector)∴Dopingshouldbehighenoughtomeetthecurrentrequirement:Nj/qvsj---Currentdensity,vs—Theelectronscattering-limitedvelocity(∼107cm/sec)2.Fullyrecessedoxideisolation--keyoftheisoplanarprocess(developedfirstbyFairchild)¾Padoxidegrowth(forstressrelease)¾CVDSi3N4deposition¾Lithography¾Etching:Si3N4+SiO2+Si9OxidationconsumedthicknessofSi:tSi=0.44tSiO2∴NeedetchSi:tSi=0.56tSiO2¾Channel-stopimplant(B+)¾Thermaloxidation3.BaseformationbyB+ionimplantationTworegionsofbase:*Intrinsic(active)base—regionbelowemitter;*Extrinsicbase—regionbelowcontactareaIntrinsicbaseimplant:¾Forlargercurrentgain—lowerdose(∼1012cm-2)preferred→baseconcentrationof∼1017cm-3¾Nottoolowdose—TopreventBCjunctionpunch-throughcurrent¾DeeperimplantandthinnerbaseExtrinsicbaseimplant:¾Foralowresistancepathtotheactivebaseregion¾Definedifferentregionofintrinsic&extrinsicbasewithemitterbyresist/mask/lithographyprocess¾Higherdoseandshallowimplant(∼1018cm-3)¾Nottoohighdose—toavoidexcessivelaterale-bcapacitanceandbreakdown4.EmitterformationAbruptandshallowemitter—necessaryforhighperformanceIC:ND1020cm-3,xj∼10-2-10-1μmChoiceofthedonor:AsbetterthanP,QD∼1015-1016cm-2Washed-emittercontactformationprocess—aself-alignedtechnique¾Emitterwashingprocess—toremovethinoxideoveremitterbywetetchingindilutedHFsolution¾Emitterareareductionbyafactorofabout3Poly-Siemitterprocess—shallowemitterformationbydiffusionfromn+-Poly-Si¾Highercurrentgain(3-7times)duetolowrecombinationrateatpolySi/Sicontactinterface¾Higherdevicedensity(emittermin.lithographyfeature)¾Highercut-offfrequencyTherearevariousmodelstoexplainthemechanismofPoly-Siemitter.Oneofthem---IncaseofAlemittercontact:Al/Siinterface—infiniterecombinationvelocity→steeperholegradientinemitter→higherbasecurrent→lowercurrentgain;ForPoly-Siemitter:Muchlowerrecombinationvelocity→smallerholegradientinemitter→smallerbasecurrent→highercurrentgain)XjEB=0.2umPn(x)n+polyEmitterBasen+Sip-SiPolyPd2SiAl0IIIPoly-Siself-aligned(PSA)processforbipolarVLSItechnologyFormationofbasecontactregion(P+)andN+emitterbyimplantanddiffusionwithapoly-Siprocess¾As+implantintodepositedpoly-Siafterintrinsicbaseimplant/formation¾Oxidedepositionandoxide/poly-Silithographyforemitterdefinition¾B+implantforextrinsicbaseafteroxidespacerformation¾Self-alignedsilicidecontactformationandmetallizationPSAprocessusingdummynitrideemittertoformself-alignedintrinsicbaseandemitter¾Nitridefilmdepositionanddummyemitterformationwithside-wallspacer¾High-doseB+implanttoformextrinsicbaseregion,P++¾SidewallremovalandB+implanttoformmedium-dopedextrinsicbaseregion,P+¾NitrideremovalandintrinsicbasedopingbylowerdoseB+implant¾n+poly-Sidepositionandself-alignedemitterformationDoublepoly-Siself-alignedbipolarprocesstechnologya)SequentialCVDdepositionofB-dopedpoly-SiandSiO2b)LithographandRIE(reactiveionetching)c)ThermalandCVDSiO2depositionandextrinsicbasediffusionfromp+-poly-Sid)RIESiO2etchingtoformside-wallandB+implanttoformintrinsicbasee)Poly-Sideposition,As+implanttoformemitter¾Self-alignedformationofbase,baseelectrode,emitterandemittercontact¾Higherdensityandhigherfrequency¾Ithasbeencalledsuperself-alignedbipolarprocesstechnology(SST)IV.SBDclampsforbetterspeedperformanceofbipolarlogicIC(STTL,LST
本文标题:半导体工艺-复旦大学-蒋玉龙-Chapter-4
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