复旦半导体工艺教材Chapter-3

Chapter3CMOSProcessTechnologyOutlineI.EvolutionofSiMOSFETII.SisubstrateselectionforMOSdevicesIII.BasicstructureandadvantageofCMOSIV.FormationoftwotypesMOSFETsonthesameSisubstrateV.CMOSDeviceisolationVI.AtypicalCMOSfabricationprocessflowVII.Latch-upeffectinCMOSdevicesVIII.Sub-micronCMOSdeviceengineeringoptimizationI.WellengineeringII.ChannelengineeringIII.Source/draindopingengineeringIV.Salicide(Self-alignedsilicide)processengineeringI.EvolutionofSiMOSFET(MISFET,IGFET)DiscoveryofMOStransistor(1928-1960)IdeaofJ.Lilienfeldandhispatent:“Deviceforcontrollingelectriccurrent”(Filed-March25,1928;patentissued-march7,1933)MISFETstructureofLilienfeld:Al/Al2O3/CuSSubstrate:CuS(semiconductor)Dielectricgate:Al2O3(10-4mm)Gateelectrode:Al(100V)Electricfield:100V/10-4mm=107V/cm(ClosetothepresentSiMOSFET!)FirstSiMOSFETwasbuiltin1960byKahngandAttala(BellLab.)CuSSGDAl2O3Al1960-1970:BasicmaterialandprocessR&DdevelopedforMOStechnology1961MOSC-Vtechnique(byTermanandMoll)1962PMOS(FSC);NMOS(RCA)1963CMOS(F.Wanlass&C.T.Sah(萨支唐)ofFSC)1966The1stCMOSICswerefabricatedSiO2/Siinterfacestudy,mobileioncontrol,…1970-2006rapidgrowthofMOStechnologyandindustryfromSSItoVLSI/ULSI/SoCMainrequirementsofMOSFETforICStableanduniformthresholdvoltage(VT)Largeandstabledrivingcurrent(ID)-highsurfacecarriermobilityLowleakage/sub-thresholdcurrentLargetransconductance(gm=dID/dVG)Highswitchingspeed/lowRCproductLong-termreliabilityLowvoltage,lowpoweroperationII.SisubstrateselectionforMOSdevicesWaferorientation:Si(100)LowinterfacetrapdensityNit(111)/Nit(100)10HighersurfacecarriermobilityS(100)S(111)DopinglevelForlowerS/Dtosubstratecapacitance(CSB,CDB)LightdopingispreferredTopreventpunch-throughproblemWidthofthePNjunctiondepletionregionSi—DielectricconstantofSi(11.9)0—Freespacepermittivity(8.85·10-14F/cm)Vbi—Built-involtage:Vbi=0.56+KT/qln(NA/ni)V—Reversebias(0)NB—SubstratedopingconcentrationIfWdLg(channellength)punch-throughThepunch-throughvoltage:VPTLg2qNB/2Si02/10))(2(BbiSidqNVVWSubstratedopinglevelshouldbeselectedproperlyforoptimizationCompromiseUsingepitaxialmaterial:p/p+ByionimplanttosetproperdopingprofileIII.BasicstructureandadvantageofCMOSCMOSinverter—basicelementofCMOSICVINMOSPMOSVOIDDVIVTNOffOnVDD0VIVDD-VTPOnOff00VTNVIVDD-VTPTrans.Trans.Trans.0LowpowerdissipationNocurrentatstaticstate‘1’or‘0’DuringVI:‘1’‘0’PMOSTr.turnsonandprovidesalowimpedancepathtochargeCLNMOSTr.turnsoffandhasaveryhighimpedance*DuringVI:‘0’‘1’NMOSTr.turnsonandprovidealowimpedancepathtodischargeCLPMOSTr.turnsoffandverylittlesupplycurrentisaddedtothedischargecurrent10offononoffCLI0101onoffoffonCL10IPowerdissipationisverylowOnly1-10%powerofNMOSgateatthesamespeedperformanceDCPowerdissipationleakage---negligiblesmall(10-9A)ACPowerdissipation:Charging+Dischargingcurrentofloadcapacitance(CL)P=CLVDD2fswitch*Halfoftheenergy(CLVDD2)isdissipatedintheP-ch.deviceduringcharging;*AnotherhalfisstoredinCL,laterdissipatedthroughNMOSTr.IV.FormationoftwotypesMOSFETsonthesameSisubstrateVariousCMOStechnologyP-well(tub)technology–firstdevelopedCMOSprocessN-welltechnology—compatiblewithNMOStechnologyTwinwelltechnology—formationN-wellandP-wellonaverylightlydopedepitaxiallayerorsubstrateProblemsofsinglewellCMOSdevicesDopinglevelisabout10timeshigherinthewellthansubstrateIncreaseS/DPNjunctioncapacitanceIncreasebodyeffectonVTHTwinwellBetterdopingoptimizationofbothNMOSandPMOSdevicesDopingprofileinwelliscriticaltoadjustVTHandotherdeviceparametersWellengineeringforadvancedCMOS!VarietyofdifferentCMOSfabricationprocesseshasbeendevelopedandunderdevelopmentbysemiconductorcompaniesandresearch/developmentinstitutionsSelf-alignedtwinwellCMOSprocessUse-Si/N+substrate*Bettercontrolofimpurityprofile*Eliminatelatch-upandbodyeffectProcess:---Siepilayergrowth--SiO2/Si3N4andwellmasklithography--N-wellimplant:P+--LocaloxidationofN-wellregion--P-wellimplant:B+--Impuritydriving-simultaneousformationofP-well&N-well--LOCOSprocessforfieldoxide--Thresholdadjustmentimplants--Gateoxideandpoly-Sigateprocess--Non-selectivep+implant(BF2)--SelectiveN+implanttoformS/DregionofN-channeldevices(As+)--Phosphorusglassdepositionandre-flow--ContactandinterconnectionprocessV.CMOSDeviceisolationElectricalisolationneededbetweendevicesandhassignificanteffectonICintegrationdensityandCMOSperformanceLocalOxidationofSilicon(LOCOS)ModifiedLOCOSNon-LOCOSisolationLocalOxidationofSilicon(LOCOS)—AverysuccessfuldeviceisolationtechnologyforbothMOSandbipolarICLOCOS---Selectivethickoxidegrowthtechnique,basedonoxidationmaskingabilityofSi-nitrideSi3N4OxidationrateofSi3N4/Si1/30(ForwetoxidationwithH2Osourceat95C)Si3N4ComsumptionduringoxidationatdifferentTSemi-recessedoxideisolationPadoxidegrowth:SiO2withcertainthicknessrequiredtoreleasestressfromSi3N4andtoavoiddislocationgenerationinSiCVDSi3N4depositiontoathicknessenoughtomasktheactiveregionfromoxidegrowthLithographypatterntodefineactiveandfieldregionsSi3N4etchingoverfieldregionChannel-stopionimplantClean