AX88772中文资料

ASIXELECTRONICSCORPORATIONReleasedDate:6/21/20054F,NO.8,HsinAnnRd.,Science-BasedIndustrialPark,Hsin-ChuCity,Taiwan,R.O.C.TEL:[phone]FAX:[phone]:AX88772_07/6/21/05Features•SinglechipUSBto10/100FastEthernetandHomePNAandHomePlugNetworkController•Integrateson-chip10/100MbpsFastEthernetPHY•USBspecification1.0and1.1and2.0compliant•SupportsUSBFullandHighSpeedmodeswithBuspowercapability•Supports4endpointsonUSBinterface•HighperformancepackettransferrateoverUSBbususingproprietarybursttransfermechanism(submittedforUSpatentapplication)•IEEE802.310BASE-Tand100BASE-TXcompatible•Embedded20KBSRAMforRXpacketbufferingand8KBSRAMforTXpacketbuffering•Supportsbothfull-duplexandhalf-duplexoperationinFastEthernet•ProvidesoptionalMIIinterfaceforEthernetPHYandHomePNA/HomePlugPHYinterface•SupportsSuspendmodeandRemoteWakeupviaLink-up,Magicpacket,orexternalpin•OptionalPHYpowerdownduringSuspendmode•Supports256/512bytes(93c56/93c66)ofserialEEPROM(forstoringUSBDescriptors)•SupportsautomaticloadingofEthernetID,USBDescriptorsandAdapterConfigurationfromEEPROMafterpower-oninitialization•ExternalPHYloop-backdiagnosticcapability•Integrateson-chip3.3Vto2.5Vvoltageregulatorandrequiresonlysinglepowersupply:3.3V•Smallformfactorwith128-pinLQFPpackage•12MHzand25Mhzclockinputfromeithercrystaloroscillatorsource•Operatingtemperaturerange:0°Cto70°C.*IEEEisaregisteredtrademarkoftheInstituteofElectricalandElectronicEngineers,Inc.*Allothertrademarksandregisteredtrademarkarethepropertyoftheirrespectiveholders.ProductDescriptionTheAX88772USBto10/100FastEthernet/HomePNA/HomePlugcontrollerisahighperformanceandhighlyintegratedASICwithembedded28KBSRAMforpacketbuffering.ItenableslowcostandaffordableFastEthernetnetworkconnectiontodesktop,notebookPC,andembeddedsystemusingpopularUSBports.IthasanUSBinterfacetocommunicatewithUSBhostcontrollerandiscompliantwithUSBspecificationV1.0,V1.1andV2.0.Itimplements10/100MbpsEthernetLANfunctionbasedonIEEE802.3,andIEEE802.3ustandardsorHomePNAstandard.Itintegratesanon-chip10/100MbpsEthernetPHYtosimplifysystemdesignandprovidesanoptionalmedia-independentinterface(MII)forimplementingFastEthernetandHomePNAfunctions.SystemBlockDiagramAlwayscontactASIXforpossibleupdatesbeforestartingadesign.Thisdatasheetcontainsnewproductsinformation.ASIXELECTRONICSreservestherightstomodifyproductspecificationwithoutnotice.Noliabilityisassumedasaresultoftheuseofthisproduct.Norightsunderanypatentaccompanythesaleoftheproduct.USBI/FAX[phone]PHY(FX)MagneticRJ45RJ11EEPROMHomeLANPHYMagneticRJ45MagneticAX88772USBto10/100FastEthernet/HomePNAControllerTableofContents1.0INTRODUCTION................................................................................................................41.1GENERALDESCRIPTION...........................................................................................................41.2AX88772BLOCKDIAGRAM....................................................................................................41.3AX88772PINOUTDIAGRAM...................................................................................................52.0SIGNALDESCRIPTION....................................................................................................63.0FUNCTIONDESCRIPTION............................................................................................103.1USBCOREANDINTERFACE..................................................................................................103.210/100ETHERNETPHY.........................................................................................................103.3MACCORE...........................................................................................................................103.4STATIONMANAGEMENT(STA).............................................................................................103.5MEMORYARBITER................................................................................................................113.6USBTOETHERNETBRIDGE...................................................................................................113.7SERIALEEPROMLOADER...................................................................................................113.8GENERALPURPOSEI/O..........................................................................................................114.0SERIALEEPROMMEMORYMAP...............................................................................124.1DETAILEDDESCRIPTION........................................................................................................135.0USBCONFIGURATIONSTRUCTURE.........................................................................165.1USBCONFIGURATION...........................................................................................................165.2USBINTERFACE....................................................................................................................165.