VHDL设计七人表决器

1FPGA1021VHDL234477LED1LED0LEDLEDLEDLEDLEDK1K71LED0LEDLEDLED1LED1LED11QUARTUSII2VHDLFileVHDL3VHDLVHDL4VHDL35VHDL6LEDFPGA171FPGACLKC13CLRP25K1K1H8K2K2J8K3K3J9K4K4A4K5K5B4K6K6A5K7K7B5ResultLEDLED1G13LED0LEDLED2G15LED1LEDLED3G14LED2LEDLED4H12LED3LEDLED5H11LED4LEDLED6J10LED5LEDLED7L9LED6LEDLED8H10LEDAG0AF13LEDAG1BF14LEDAG2CF15LEDAG3DE15LEDAG4EF16LEDAG5FF17LEDAG6GE184VHDLLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYBJQISPORT(CLK,CLR:INSTD_LOGIC;----CLKCLRK:INSTD_LOGIC_VECTOR(6DOWNTO0);----Result:OUTSTD_LOGIC;----LEDAG,LED:OUTSTD_LOGIC_VECTOR(6DOWNTO0));----LEDAGLEDENDENTITYBJQ;ARCHITECTUREoneOFBJQISBEGINPROCESS(K)VARIABLEshu:INTEGER;----shuBEGINIF(CLR='1')THEN----LED=K;----shu:=0;IFCLK'EVENTANDCLK='1'THENIFK(0)='1'THENshu:=shu+1;ENDIF;IFK(1)='1'THENshu:=shu+1;ENDIF;IFK(2)='1'THENshu:=shu+1;ENDIF;IFK(3)='1'THENshu:=shu+1;ENDIF;IFK(4)='1'THENshu:=shu+1;ENDIF;IFK(5)='1'THENshu:=shu+1;ENDIF;IFK(6)='1'THENshu:=shu+1;ENDIF;5CASEshuiS----WHEN0=Result='0';LEDAG=0111111;LED=K;WHEN1=Result='0';LEDAG=0000110;LED=K;WHEN2=Result='0';LEDAG=1011011;LED=K;WHEN3=Result='0';LEDAG=1001111;LED=K;WHEN4=Result='1';LEDAG=1100110;LED=K;WHEN5=Result='1';LEDAG=1101101;LED=K;WHEN6=Result='1';LEDAG=1111101;LED=K;WHEN7=Result='1';LEDAG=0100111;LED=K;WHENothers=Result='0';LEDAG=0000000;LED=K;ENDCASE;ENDIF;ELSE-----Result='0';LEDAG=0111111;LED=0000000;ENDIF;ENDPROCESS;ENDARCHITECTUREone;6VHDL7K0-K71LEDLED2LED8LEDLEDLED1LED1