xapp224[1]

XAPP224(v2.5)July11,2005©2002-2005Xilinx,Inc.Allrightsreserved.AllXilinxtrademarks,registeredtrademarks,patents,andfurtherdisclaimersareaslistedat:Xilinxisprovidingthisdesign,code,orinformationasis.Byprovidingthedesign,code,orinformationasonepossibleimplementationofthisfeature,application,orstandard,Xilinxmakesnorepresentationthatthisimplementationisfreefromanyclaimsofinfringement.Youareresponsibleforobtaininganyrightsyoumayrequireforyourimplementation.Xilinxexpresslydisclaimsanywarrantywhatsoeverwithrespecttotheadequacyoftheimplementation,includingbutnotlimitedtoanywarrantiesorrepresentationsthatthisimplementationisfreefromclaimsofinfringementandanyimpliedwarrantiesofmerchantabilityorfitnessforaparticularpurpose.SummaryDatarecoveryallowsareceivertoextractembeddedclockdatafromanincomingdatastream.Thereceiverusuallyextractsthedatafromtheincomingclock/datastreamandthenmovesthisdataintoaseparateclockdomain.Sometimes,thereceiver’sclockisalsousedforonwarddatatransmission.Thecircuitdescribedinthisapplicationnoteprovidesapartialsolutionatdataratesupto160Mb/sinaVirtex™-E-7deviceandaSpartan™-IIE-6device,upto320Mb/sforaSpartan-3-4device,andupto420Mb/sinaVirtex-II-5deviceoraVirtex-IIPro-6device.Thesolutionispartialinthesensethatnoclockisactuallyrecovered,butthedataarrivingisfullyextracted.ThespeedislimitedbythemaximumfrequencythatcanbeacceptedbytheDataLockedLoop(DLL),inamodewheretheDLLiscapableofprovidingbothanewclock,andanotherclockshiftedby90degrees.AtypicalapplicationisshowninFigure1.IntroductionThecircuitdescribedhereinusesaclock(localoscillator)thatisrunningatthesamenominalfrequencyofthedatastreambeingdecoded.Typically,thismeansthatthelocaloscillatoriseitherslightlyfasterorslightlyslowerthantheincomingclock/datastream.Forexample,atypicallinkmayberunningat400MHzplusorminusasmallbutdifferentvariation.Theactualperformancerelativetotheclockratewillbediscussedaftergivingadescriptionofhowthecircuitworks.Assumingthattheincomingclock/datalineisnotencodedbeyonda1beingtransmittedaslineHighanda0aslineLow.Minimumtransitionrequirementsarediscussedinthefollowingsections.ApplicationNote:Virtex,Virtex-II,Spartan-IIE,andSpartan-3SeriesXAPP224(v2.5)July11,2005DataRecoveryAuthor:NickSawyerRFigure1:TypicalDataRecoveryApplicationCLK0CLK90VirtexSeriesFPGAX224_01_010202DLLSystemClock(420MHz)DataRecoveryDataRecoveryDataRecoveryDataRecoverySerialLink1SerialLink2SerialLink3420Mb/sSerialLinksSerialLinkn2(v2.5)July11,2005DataRecoveryRFortheVirtex-EdeviceorforaslowlinkusingaVirtex-IIdevice,theincomingsystemclockisfedtoaDLLcomponent,andtheDLLCLK0isusedtoprovideaclock(CLK)forthesynchronizercircuit,aswellasfeedbackfortheDLL.Anotherversionoftheinputclockdelayedby90degrees(CLK90)andsynchronizedwiththeoriginalclockisavailable.ForafastlinkusingtheVirtex-IIdevice,twoDLL(DCM)modulesarerequired(seeFigure2);oneprovidestheCLKandtheotherprovidesCLK90,usingthefixedphaseshiftfeatureavailabletotheVirtex-IIdevice.Figure2:ClockGenerationUsingOneorTwoDLLs/DCMsCLKCLK90ClockInCLKCLK90CLKClockInCLKCLK90CLKPhaseshift=64Phaseshift=0Virtex-EorSpartan-IIEDeviceor‘Slow’Virtex-II,Virtex-IIPro,orSpartan-3Device‘Fast’Virtex-II,Virtex-IIPro,orSpartan-3DeviceX224_06_030204DataRecoveryXAPP224(v2.5)July11,2005(onerisingedgeandonefallingedge)andtwobyCLK90(risingandfallingedges).Itisimportantthatthedelayfromtheinputpintothesefourflip-flopsbealmostequal.ThisiseasilyachievedbygivingthesoftwareaMAXSKEWparameterforthisnet,of500ps,forexample.Theabsolutedelayisirrelevant;onlytheskewisimportant.Thefirstflip-flopisclockedbytherisingedgeoftheclockdescribedastimedomainA.ThesecondflipflopisclockedbytherisingedgeCLK90(timedomainB);thethirdflipflopisclockedonthefallingedgeofCLK(timedomainC);andthefourthisclockedonthefallingedgeCLK90(timedomainD).Asshowninthetimingdiagram(Figure3),thisgivesfourdatasamplepoints,eachseparatedby90degreesoftheoriginalclockfrequency.Inthecaseofa420MHzsystemclock,thislogiciseffectivelyrunningat1680MHz.Thesefoursamplepointsarethenclockedoncemore,toremoveanymetastabilityissuesandtomovethemintothesametimedomain.Thisactuallytakesplaceintwoorthreestages(againtoavoidanyfourtimesclockfrequencylogicpaths).Figure3:TimingDiagramABCDCLKCLK90CASE1DataCASE2DataCASE3DataCASE4Datax224_02_0130014(v2.5)July11,2005DataRecoveryRInthefirstdecisionstage,showninFigure5,thecircuitdetectstransitionsonthedatalines.ThesignalsAAPtoDDPrecognizepositivetransitions,andthesignalsAANtoDDNrecognizenegativetransitions.Eightsignalsarenowavailableforthedecisionprocess.Fourmutuallyexclusivesignalscannowbedecoded,whereonlyonetransitionsHighwheneverthereisadatatransition.Thesef