STM32F10xxCDE局限性列表(2010年6月第8版英文)

June2010DocID14732Rev81/37STM32F101xC/D/EandSTM32F103xC/D/EErratasheetSTM32F101xC/D/EandSTM32F103xC/D/Ehigh-densitydevicelimitationsSiliconidentificationThiserratasheetappliestotherevisionsZandYoftheSTMicroelectronicsSTM32F101xC/D/EaccesslineandSTM32F103xC/D/Eperformancelinehigh-densityproducts.ThesefamiliesfeatureanARM™32-bitCortex®-M3core,forwhichanerratanoticeisalsoavailable(seeSection1fordetails).ThefulllistofpartnumbersisshowninTable2.TheproductsareidentifiableasshowninTable1:●bytheRevisioncodemarkedbelowtheordercodeonthedevicepackage●bythelastthreedigitsoftheInternalordercodeprintedontheboxlabelTable1.DeviceIdentification(1)1.TheREV_IDbitsintheDBGMCU_IDCODEregistershowtherevisioncodeofthedevice(seetheSTM32F10xxxreferencemanualfordetailsonhowtofindtherevisioncode).OrdercodeRevisioncode(2)markedondevice2.RefertoAppendixA:RevisioncodeondevicemarkingfordetailsonhowtoidentifytheRevisioncodeonthedifferentpackages.STM32F103xC,STM32F103xD,STM32F103xE“Z”or“Y”STM32F101xC,STM32F101xD,STM32F101xE“Z”or“Y”Table2.DevicesummaryReferencePartnumberSTM32F101xCDESTM32F101RCSTM32F101VCSTM32F101ZCSTM32F101RDSTM32F101VDSTM32F101ZDSTM32F101RESTM32F101VESTM32F101ZESTM32F103xCDESTM32F103RCSTM32F103VCSTM32F103ZCSTM32F103RDSTM32F103VDSTM32F103ZDSTM32F103RESTM32F103VESTM32F103ZE™32-bitCortex®-M3limitations...........................71.1Cortex-M3limitationsdescriptionforSTM32F10xxxhigh-densitydevices71.1.1Cortex-M3LDRDwithbaseinlistmayresultinincorrectbaseregisterwheninterruptedorfaulted...................................81.1.2Cortex-M3eventregisterisnotsetbyinterruptsanddebug..........81.1.3Cortex-M3BKPTindebugmonitormodecancauseDFSRmismatch..81.1.4Cortex-M3mayfreezeforSLEEPONEXITsingleinstructionISR......92STM32F10xxxsiliconlimitations..............................102.1VoltageglitchonADCinput0..................................122.2FlashmemoryreadafterWFI/WFEinstruction....................122.3Debugregisterscannotbereadbyusersoftware..................122.4DebuggingStopmodeandsystemticktimer......................132.5DebuggingStopmodewithWFEentry..........................132.6Alternatefunction...........................................132.6.1USART1_RTSandCAN_TX.................................132.6.2SPI1inslavemodeandUSART2insynchronousmode............142.6.3SPI1inmastermodeandUSART2insynchronousmode..........142.6.4SPI2inslavemodeandUSART3insynchronousmode............142.6.5SPI2inmastermodeandUSART3insynchronousmode..........152.6.6SDIOwithTIM8...........................................152.6.7SDIOandTIM3_REMAP....................................152.6.8SDIOwithUSART3remappedandUART4......................162.6.9FSMCwithI2C1andTIM4_CH2..............................162.6.10FSMCwithUSART2remapped...............................162.6.11FSMCwithUSART3andTIM1remapped.......................172.6.12I2S2inmaster/slavemodeandUSART3insynchronousmode......172.6.13USARTx_TXpinusage.....................................172.7PVDandUSBwakeupevents.................................182.8SPI3inI2Sslavemode:timingsensitivitybetweenI2S3_WSandI2S3_CK..............................................182.9BoundaryscanTAP:wrongpatternsentoutafterthe“captureIR”state.182.10FlashmemoryBSYbitdelayversusSTRTbitsetting...............19ErratasheetContentsDocID14732Rev83/372.11I2Cperipheral..............................................192.11.1Somesoftwareeventsmustbemanagedbeforethecurrentbyteisbeingtransferred..........................................192.11.2Wrongdatareadintodataregister............................202.11.3SMBusstandardnotfullysupported...........................202.11.4WrongbehaviorofI2CperipheralinmastermodeafteramisplacedStop........................................................212.11.5Mismatchonthe“SetuptimeforarepeatedStartcondition”timingparameter...............................................212.11.6Datavalidtime(tVD;DAT)violatedwithouttheOVRflagbeingset.....222.12SPIperipheral.............................................222.12.1CRCstillsensitivetocommunicationclockwhenSPIisinslavemodeevenwithNSShigh........................................222.12.2ParasiticTXEgenerationinSPI2/I2S2slavemode+16-bitdataframemode...................................................232.13USARTperipheral..........................................232.13.1ParityErrorflag(PE)issetagainafterhavingbeenclearedbysoftware........................................................232.13.2Idleframeisnotdetectedifreceiverclockspeedisdeviated........242.13.3Infullduplexmode,theParityError(PE)flagcanbeclearedbywritingthedataregister..............................................242.13.4ParityError(PE)flagisnotsetwhenreceivinginMutemodeusingaddressmarkdetection.....................................242.13.5BreakframeistransmittedregardlessofnCTSinputlinestatus......242.14Timers...................................................252.14.1Missingcaptureflag........................................252.14.2Overcapturedetectedtooearly.......