SR9900-Datasheet

CoreChipsShenZhenCo.,LtdSR9900BriefDatasheet2018-04-28Ver1.01/8Ultra-LowPowerSingle-ChipUSB2.0to10/100MEthernetControllerGeneralDescriptionTheSuperealSR990010/100MEthernetcontrollercombinesanIEEE802.3ucompliantMediaAccessController(MAC),USBbuscontroller,andembeddedmemory.Alinearregulator(LDO)isincorporatedforreducedBOMcost.Withstate-of-the-artDSPtechnologyandmixed-modesignaltechnology,theSR9900offershigh-speedtransmissionoverCAT5UTPcableorCAT3UTP(10Mbpsonly)cable.FunctionssuchasCrossoverDetectionandAuto-Correction,polaritycorrection,adaptiveequalization,cross-talkcancellation,echocancellation,timingrecovery,anderrorcorrectionareimplementedtoproviderobusttransmissionandreceptioncapabilities.TheSR9900featuresembeddedOne-Time-Programmable(OTP)memory.AdvancedConfigurationPowermanagementInterface(ACPI)—powermanagementformodernoperatingsystemsthatarecapableofOperatingSystem-directedPowerManagement(OSPM)—issupportedtoachievethemostefficientpowermanagementpossible.InadditiontotheACPIfeature,remotewake-up(includingAMDMagicPacketandMicrosoftWake-UpFrame)issupportedinbothACPIandAPM(AdvancedPowerManagement)environments.TheSR9900supportsMicrosoftWakePacketDetection(WPD)toprovideWake-UpFrameinformationtotheOS,e.g.,PatternID,OriginalPacketSize,SavedPacketSize,SavedPacketOffset,etc.WPDhelpspreventunwanted/unauthorizedwake-upofasleepingcomputer.TheSR9900isfullycompliantwithMicrosoftNDIS5,NDIS6(IPv4,IPv6,TCP,UDP)Checksumfeatures,andsupportsIEEE802IPLayer2priorityencodingandIEEE802.1QVirtualbridgedLocalAreaNetwork(VLAN).TheabovefeaturescontributetoloweringCPUutilization,especiallybenefitingperformancewheninoperationonanetworkserver.TheSR9900supportsProtocoloffload.ItoffloadssomeofthemostcommonprotocolstoNIChardwareinordertopreventspuriouswake-upandfurtherreducepowerconsumption.TheSR9900canoffloadARP(IPv4)andNS(IPv6)protocolswhileintheD3powersavingstate.TheSR9900supportsIEEE802.3az-2010,alsoknownasEnergyEfficientEthernet(EEE).IEEE802.3azoperateswiththeIEEE802.3MediaAccessControl(MAC)SublayertosupportoperationinLowPowerIdlemode.WhentheEthernetnetworkisinlowlinkutilization,EEEallowssystemsonbothsidesofthelinktosavepower.TheSR9900alsofeaturesUSB2.0technology.Itprovideshigherbandwidthandimprovedprotocolsfordataexchangebetweenthehostandthedevice.Inaddition,USB2.0offersamoreaggressivepowermanagementfeaturethatenablesselectivesuspendtosaveenergy.TheSR9900issuitableformultiplemarketsegmentsandemergingapplications,suchasdesktop,mobile,workstation,server,communicationsplatforms,dockingstation,andembeddedapplications.CoreChipsShenZhenCo.,LtdSR9900BriefDatasheet2018-04-28Ver1.02/8FeaturesSupportsUSB2.0and1.1Integrated10/100MtransceiverSupportsFullDuplexflowcontrol(IEEE802.3x)FullycompliantwithIEEE802.3,IEEE802.3uSupportsIEEE802.1PLayer2PriorityEncodingSupportsIEEE802.1QVLANtaggingSupportsIEEE802.3az-2010(EEE)Auto-NegotiationwithNextPagecapabilityMicrosoftAOAC(AlwaysOnAlwaysConnected)SupportsWake-UpFramepatternexactmatchingSupportslinkchangewakeupSupportsMicrosoftWPD(WakePacketDetection)SupportsProtocolOffload(ARP&NS)MicrosoftNDIS5,NDIS6ChecksumOffload(IPv4,IPv6,TCP,UDP)andSegmentationTask-offload(Largesendv1andLargesendv2)supportSupportspairswap/polarity/skewcorrectionCrossoverDetection&Auto-CorrectionStandardforsleepinghosts(seenote1)XTAL-LessWake-On-LANSupports25MHzexternalclock(fromoscillatororsystemclocksource)Supportspowerdown/linkdownpowersavingTransmit/Receiveon-chipbuffersupportEmbeddedOTPmemoryLowpowersupply1.2V3.3Vand5.0V;1.2Vand3.3Varegeneratedbyinternallinearregulator(LDO)SupportsCustomizableLEDsControllableLEDBlinkingFrequencyandDutyCycleSupportshardwareCRC(CyclicRedund-ancyCheck)functionLANdisablewithGPIOpinSupportsLPM(LinkPowerManagement)SPIFlashInterfaceSupportsCDC-ECM24-pinQFN‘Green’package0.11µmCMOSprocessApplicationUSBDongleNetworkPrinterCardReaderforpaymentDockingStationPortReplicatorforMobileComputerInternetSecurityUSBKeyMediaGatewayPocketableComputerPortableMediaPlayerTiVoBoxGameConsoleIPSTBDVD-Recorder/DVRIPTVCoreChipsShenZhenCo.,LtdSR9900BriefDatasheet2018-04-28Ver1.03/8BlockDiagramUSBPHY&CoreInternalSRAMOSC&PLLD+D-MemoryControllerTXMachineRXMachineMIIInterfaceControl&StatusRegGPIOControllerMIIManagement&ControllerEthernetPHYRegulatorSPIFlashI/FPORFigure1.BlockDiagramCoreChipsShenZhenCo.,LtdSR9900BriefDatasheet2018-04-28Ver1.04/8PinAssignmentAVDD33MDI+[0]U2GNDLANWAKEBRSETAVDD12XTAL2U2DPSPISDILED1/SPISCKDVDD12LED0/SPICSBGPIODVDD3319202122232412345618171615141312111098725GNDMDI-[1]MDI+[1]MDI-[0]U2DMXTAL1SPISDODVDD12AVDD33VDD5DVDD12_UPSFigure2.PinAssignmentsCoreChipsShenZhenCo.,LtdSR9900BriefDatasheet2018-04-28Ver1.05/8PinDescriptionsPinNoSymbolTypeDescription2,3MDI+[0]、MDI-[0]I/OInMDImode,thispairactsastheBI_DA+/-pair,andisthetransmitpairin10Base-Tand100Base-TX.InMDIcrossovermode,thispairactsastheBI_DB+/-pair,andisthereceivepairin10Base-Tand100Base-TX.4,5MDI+[1]、MDI-[1]I/OInMDImode,thispairactsastheBI_DB+/-pair,andisthereceivepairin10Base-Tand100Base-TX.InMDIcrossovermod