EPIC微体系结构的存储级并行执行模型的研究(1)

30120071CHINESEJOURNALOFCOMPUTERSVol.30No.1Jan.2007:2005206216;:2006205204.(2002AA110020)(90207011).,,1972,,.E2mail:[e-mail].,,1967,,.,,1964,,,.,,1947,,,.,,1966,,,.EPIC(410073)(MemoryLevelParallelism,MLP)OLSM(OptimizedLock2StepexecutionModel),OLSM.OLSM(ExplicitParallelInstructionComputing,EPIC),(VeryLongInstructionWord,VLIW),,MLP.;;;;TP302TheResearchonMemory2LevelParallelismExecutionModelinEPICArchitectureDENGRang2YuCHENHai2YanXINGZuo2ChengXIELun2GuoZENGXian2Jun(SchoolofComputerScience,NationalUniversityofDefenceTechnology,Changsha410073)AbstractThispaperpresentsaninstructionOptimizedLock2StepexecutionModel(OLSM)andbuildsamemoryhierarchywhichcanembodytheessenceofthismodel.InOLSMEPICmicro2processor,instructioncanbeexecutedout2of2order,soshortcomingoftraditionVLIWlock2stepexecutionisresolved.OLSMcanmakeuseoftheabundancecomputationandmemoryresourcestohidememoryaccesslatencyandimproveMemoryLevelParallelism(MLP)atbest.KeywordsEPIC;unitaccesslatency;non2unitaccesslatency;memorylevelparallelism;opti2mizedlock2stepexecutionmodel1EPICVLIW,.,(MultiOP),(PlanOfExecution,POE),VLIWPOE,,[122].VLIW,:1,,,().,,,.EPIC,,,.,,:,().,.(1)UAL(UnitAssumedLatency)RISCUAL,,.()1,,.1,,,.1(a)UAL,1(b).1UAL(2)NUALNUAL(Non2UnitAssumedLatency),(a)L,L1;(b),L-1,.NUAL,2.T1T2,T10.2NUALEQ(equals)NUAL,,.NUALLEQ(lessorequals),1,.LEQ,,.,VLIWEPICNUAL,.2NUAL211,EQ,EQ,,.,.2.2NUAL,,,,(latencystalling).P,V,(V-P),.,,.,NUAL,,,,..,.Rau,[3].,:(1),NUAL.,,,;(2),.571:EPIC,,,,.,,.,,.,,,,.(in2orderinterlock),ISA,,NUAL,.213NUAL,.(),NUAL,,,.,()(),.,.NUAL,.NUAL,,,.MultiOpNUAL,EPIC,[3].,NUAL,,,.214NUALEQ,[4].,EQ.,LEQ,,.,EQ,LEQ,.,EQ,.,.,,NUAL.,,,,,.,ILPILP.3EPICEPIC,1,.:IjIjIj.,,.,EPIC.,(executinggroup),MultiOp.(ReadAfterWrite,RAW)(WriteAfterWrite,WAW),RAWWAW,.EPIC11(4,2,23).8,FETCHPREDICTISSUERENAMEREGEXECOMMITWRB.,FETCHPREDICT,;ISSUERENAMEREGEXECOMMITWRB,.(EXE)(EXE),.,,EXE,EXE,.,EXE672007,,COMMIT,EXE(out2of2orderexecuting).,[4](in2ordercommitting).,EPIC:(1),,,.,,.(2)COMMITFIFO,.311EPIC,.Cache,1,;Cache,.,,,.,,COMMIT.3.EXEL1Cache(L1D),L2Cache,,,L1D,COMMIT.L1DL2Cache.3SBI(SystemBusInterface).3EPIC312EPICMLPEXE,.,CacheMLP(d)(w),MLPBaseD2Cache=w(d+1).MLPMLPBasemax,MLPBasemax=MLPI2Cache+MLPBaseD2Cache=MLPI2Cache+w(d+1)(1)(1),w=1,EPIC,MLPBasemax=MLPI2Cache+d+1(2)(2)w=4,MLPBasemax=MLPI2Cache+4(d+1)(3)MLPI2CacheCache,EPIC.MLP,L2Cache,,MLP.MLP,MLPBasemean.EPIC,:.Load2to2Use.Load2to2Use,Dist.MLPBasemeanDist.MLPBasemean=f:Distw=MLPI2Cache+wDist,Distd+1MLPI2Cache+w(d+1),DistEd+1(4)4OLSM,EPICEXE,MLP.RENAMEREGCOMMIT,,,.EPIC:.EPIC,COMMIT3,,1200[5],,.,771:EPIC.33COMMIT,WAWRAW,,.,:(1)EXE.(2)EXE.(3)EXE,COMMIT(CacheTLB).,:REG,COMMIT,,,COMMITWRB.EPIC,,NUAL(OptimizeLockStepExecutionModel,OLSM),(),.OLSM,4.L1D,L1D,L1D,L1DL2Cache,,L2Cache,L2Cache,(),L1D.4OLSMNUAL,,,MLP.NUALOLSMNUAL,EPICMLP,:,COMMIT,,.OLSM:(1),,,().(2),COMMIT,,,,.(3),.(4),MCA(MachineCheckAbort).(5)L1DL2Cache.411OLSMOLSM,:,,L1DCache,L2CacheCache.,[2],,.,DECAlpha21264,,,,L2CacheCache.,Cache5(a),OLSMCache5(b).5Cache412OLSMMLPOLSM,MLP,,:(1);(2)L2CachewL;(3)L2CacheSBIp.MLPMLPOLSMmax,MLPOLSMmax=MLPI2Cache+MLPOLSMD2Cache=MLPI2Cache+w(L+2)+p(5)MLPMLPOLSMmean,872007MLPOLSMmeam=f:Distw=MLPI2Cache+wDist,wDistw(L+2)+pMLPI2Cache+(w(L+2)+p),wDistEw(L+2)+p(6)5OLSMEPIC511YHFT642164,EPIC,OLSM,w=w=4,L=5,P=16,MLPI2Cache=8,MLPOLSMmax=MLPI2Cache+MLPOLSMD2Cache=52(7)YHFT6421,EPIC,w=4,d=3.512MLPmax(1)w(d+1)w(L+2)+p,MLPBasemaxMLPOLSMmax(8)(2)w(d+1)w(L+2)+p,MLPBasemaxMLPOLSMmax(9)(3)L2Cache,L2Cache,w=w,d=L,MLPBasemaxMLPOLSMmax(10)EPIC,MLPL2Cache,.,,,,d4;L2Cache,EPICOLSM,L57;L2CacheSBIFIFO,,p16.,,,MLPBasemaxMLPOLSMmax,OLSMMLPEPIC.MLPBasemax(d=3)MLPOLSMmaxCPUSPEC20006.,A(ALUMMX),EPIC,A,MLPBasemax5134.OLSM,A,EXECOMMIT,,MLPOLSMmax1812.6MLPmax513MLPmean,MLP.7,w=w,dL+p+1,OLSMDist,MLPOLSMmeanMLPBasemean.,Dist,,,Dist.,7OLSM.7EPICOLSMMLP,OLSM,loadL1D,L2CacheCache,,OLSMMLP.CPUSPEC2000,8.8:MLPBasemean1133,MLPOLSMmean4159.,OLSMEPIC,MLP,,IPC,,EPIC.8MLPmean6,971:EPICEPICMLP,MLPOLSM.OLSM,EPIC.,SPEC2000:EPIC,OLSM,()MLP.[1]ColwelRPetal.AVLIWarchitectureforatraceschedulingcompiler.IEEETransactionsonComputers,1988,37(8):9672979[2]DengRang2Yu,XieLun2Guo,XingZuo2Cheng.ExploitingmemorylevelparallelisminEPICarchitecture.JournalofComputerResearchandDevelopment,2004,41(Supplement):2592264(inChinese)(,,.EPIC.,2004,41():2592264)[3]SchlanskerMS,RauBR.EPIC:Anarchitectureforinstruc2tion2levelparallelprocessors.HPLTechnicalReport:HPL219992111,2000[4]SchlanskerMS,RauBR.EPIC:Explicitlyparallelinstruc2tioncomputing.IEEEMicro,2000,33(4):44258[5]SamuelDNaffziger,GlennColon2Bonetetal.Theimplemen2tationoftheitanium2microprocessor.IEEEJournalofSolid2StateCircuits,2002,37(11):24232DENGRang2Yu,bornin1972,as2sociateprofessor.Hisresearchinterestsincludehighperformancecomputersys2tem,micro2architectureandmicro2elec2tronicsdesign.CHENHai2Yan,bornin1967,associateprofessor.Herresearchinterestismicro2architecture.XINGZuo2Cheng,bornin1961,professor.Hisre2searchinterestsincludemicro2professorandmicro2electronicsdesign.XIELun2Guo,bornin1947,professor.Hisresearchinterestsincludehigh