EDA技术使用教程课后答案(第三版)潘松版

1-1EDAASICFPGA?P3~4EDAASICFPGACPLDFPGACPLDICASICFPGACPLDEDASoCASIC1-2VHDL?P6CPUCPUCPUVHDLVHDLVHDL()l-3???P5??(1)VHDL(2)(RegisterTransportLevelRTL)(3)RTL()(4)(ASIC)FPGA?1-3VHDLVHDL1-4EDA?P7~10EDA1-5IPEDA?P11~12IP2-1EDAFPGA/CPLDP13~161.(/HDL)2.3.4.5.6.2-2IP?IPEDA?P24~26IP?IPASICFPGA/CPLDIPEDA?IPEDAEDAIPIPIPIPVHDLIPHDLIPIP2-3ASICP18~19ASIC,(Semi-custom)(Full-custom)2-4FPGA/CPLDASIC?P16,18FPGA/CPLDASICASIC2-5FPGA/CPLDEDAEDAP19~23FPGA/CPLDEDAEDAHDLHDLHDL3-1OLMC?GALP34~36OLMC?OLMCGAL?GALOLMC3-2?P33~3440GALCPLDPAL3-3?P40~41FPGA3-4FPGALAB?P43~45FPGACyclone/CycloneIILABEABI/OPLLLABLEFPGALAB3-5?P47~50BSTIC3-6P58EEPROMFlashCPLDCPLDSRAMSRAMSRAMFPGASRAMFPGA3-7PLDCPLDPLDFPGAAPEXPLD?MAXIIPLD??P54~56APEX(AdvancedLogicElementMatrix)FPGAPLDSRAMMAXIICPLDPLDEEPROM4-1ENTITYbuf3sIS--1PORT(input:INSTD_LOGIC;--enable:INSTD_LOGIC;--output:OUTSTD_LOGIC);--ENDbuf3x;ENTITYmux21IS--221PORT(in0,in1,sel:INSTD_LOGIC;output:OUTSTD_LOGIC);4-1.4-2.3-3041IF_THENCASEVHDLs1s0STD_LOGIC_VECTORs1='0's0='0's1='0's0='1's1='1's0='0's1='1's0='1'y=ay=by=cy=d4-2.LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX41ISPORT(s:INSTD_LOGIC_VECTOR(1DOWNTO0);--a,b,c,d:INSTD_LOGIC;--y:OUTSTD_LOGIC);--ENDENTITY;ARCHITECTUREARTOFMUX41ISBEGINPROCESS(s)BEGINIF(S=00)THENy=a;ELSIF(S=01)THENy=b;ELSIF(S=10)THENy=c;ELSIF(S=11)THENy=d;ELSEy=NULL;ENDIF;EDNPROCESS;ENDART;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX41ISPORT(s:INSTD_LOGIC_VECTOR(1DOWNTO0);--a,b,c,d:INSTD_LOGIC;--y:OUTSTD_LOGIC);--ENDMUX41;ARCHITECTUREARTOFMUX41ISBEGINPROCESS(s)BEGINCASEsISWHEN00=y=a;WHEN01=y=b;WHEN10=y=c;WHEN11=y=d;WHENOTHERS=NULL;ENDCASE;ENDPROCESS;ENDART;4-3.3-3121MUXKMUX21As='0''1'y='a'y='b'CASE21MUX21A4-3.LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMUX221ISPORT(a1,a2,a3:INSTD_LOGIC_VECTOR(1DOWNTO0);--s0,s1:INSTD_LOGIC;outy:OUTSTD_LOGIC);--ENDENTITY;ARCHITECTUREONEOFMUX221ISSIGNALtmp:STD_LOGIC;BEGINPR01:PROCESS(s0)BEGINIFs0=0THENtmp=a2;ELSEtmp=a3;ENDIF;ENDPROCESS;PR02:PROCESS(s1)BEGINIFs1=0THENouty=a1;ELSEouty=tmp;ENDIF;ENDPROCESS;ENDARCHITECTUREONE;ENDCASE;4-4.DVHDL4-4.LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMULTIISPORT(CL:INSTD_LOGIC;--CLK0:INSTD_LOGIC;--OUT1:OUTSTD_LOGIC);--ENDENTITY;ARCHITECTUREONEOFMULTIISSIGNALQ:STD_LOGIC;BEGINPR01:PROCESS(CLK0)BEGINIFCLKEVENTANDCLK=1THENQ=NOT(CLORQ);ELSEENDIF;ENDPROCESS;PR02:PROCESS(CLK0)BEGINOUT1=Q;ENDPROCESS;ENDARCHITECTUREONE;ENDPROCESS;4-5.1VHDL(1)13-32h_suberdiffs_outsub_in(2)18(xy-sun_in=diffr)4-5.1or2a.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYor2aISPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDENTITYor2a;ARCHITECTUREoneOFor2aISBEGINc=aORb;ENDARCHITECTUREone;2h_subber.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYh_subberISPORT(x,y:INSTD_LOGIC;diff,s_out::OUTSTD_LOGIC);ENDENTITYh_subber;ARCHITECTUREONEOFh_subberISSIGNALxyz:STD_LOGIC_VECTOR(1DOWNTO0);BEGINxyz=x&y;PROCESS(xyz)BEGINCASExyzISWHEN00=diff='0';s_out='0';WHEN01=diff='1';s_out='1';WHEN10=diff='1';s_out='0';WHEN11=diff='0';s_out='0';WHENOTHERS=NULL;ENDCASE;ENDPROCESS;ENDARCHITECTUREONE;f_subber.VHDLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYf_subberISPORT(x,y,sub_in:INSTD_LOGIC;diffr,sub_out:OUTSTD_LOGIC);ENDENTITYf_subber;ARCHITECTUREONEOFf_subberISCOMPONENTh_subberPORT(x,y:INSTD_LOGIC;diff,S_out:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor2aPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALd,e,f:STD_LOGIC;BEGINu1:h_subberPORTMAP(x=x,y=y,diff=d,s_out=e);u2:h_subberPORTMAP(x=d,y=sub_in,diff=diffr,s_out=f);u3:or2aPORTMAP(a=f,b=e,c=sub_out);ENDARCHITECTUREONE;ENDARCHITECTUREART;4-6.MX3256.VHDVHDL4-6.MAX3256LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYMAX3256ISPORT(INA,INB,INCK:INSTD_LOGIC;INC:INSTD_LOGIC;E,OUT:OUTSTD_LOGIC);ENDENTITYMAX3256;ARCHITECTUREONEOFMAX3256ISCOMPONENTLK35--LK35PORT(A1,A2:INSTD_LOGIC;CLK:INSTD_LOGIC;Q1,Q2:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTD--DPORT(D,C:INSTD_LOGIC;CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTMUX21--PORT(B,A:INSTD_LOGIC;S:INSTD_LOGIC;C:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALAA,BB,CC,DD:STD_LOGIC;BEGINu1:LK35PORTMAP(A1=INA,A2=INB,CLK=INCK,Q1=AA,Q2=BB);u2:DPORTMAP(D=BB;CLK=INCK,C=INC,Q=CC);u3:LK35PORTMAP(A1=BB,A2=CC,CLK=INCK,Q1=DD,Q2=OUT1)u4:MUX21PORTMAP(B=AA,A=DD,S=BB,C=E);ENDARCHITECTUREONE;164-7.LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT16ISPORT(CLK,RST,EN:INSTD_LOGIC;CHOOSE:INBIT;SETDATA:BUFFERINTEGERRANCE65535DOWNTO0;COUT:BUFFERINTEGERRANCE65535DOWNTO0);ENDCNT16;ARCHITECTUREONEOFCNT16ISBEGINPROCESS(CLK,RST,SDATA)VARIABLEQI:STD_LOGIC_VECTOR(65535DOWNTO0);BEGINIFRST='1'THEN--QI:=(OTHERS='0');ELSIFSET=1THEN--QI:=SETDATA;ELSIFCLK'EVENTANDCLK='1'THEN--IFEN=1THENIFCHOOSE=1THEN--QI:=QI+1;--ELSEQI=QI-1;--ENDIF;ENDIF;ENDIF;COUT=QI;--ENDPROCESS;ENDONE;5-1QuartusIIVHDLSignalTapIIP95~P11512345678SignalTapII9SignalTapII10SignalTapII11SignalTapII12SignalTapII13SignalTapII14SignalTapII5.65.75.85.95.105.125.135.146-1??P