Synplicity培训以及试验相关资料

1AdvancedSynthesiswiththeSynplifyProÒToolWinter/Spring20032CourseOutlineCourseOutline»Introduction»HDLCodingforPerformanceLab1»TechnologyIndependentAttributes»TechnologySpecificAttributesLab3»AdvancedSynthesisTopicsforAlteraCPLD»ComplexClocking»RetimingLab2Lab4Lab5»AdvancedSynthesisTopicsforXilinxFPGA»MultiPointSynthesisFlow23IntroductionIntroductionIntroduction»Introduction»HDLCodingforPerformance4Synplicity’sSolutionsSynplicity’sSolutionsCertify®Amplify®PhysicalOptimizer™SynplifyPro®andSynplify®SynplifyASIC®ASICsolutionsFPGAsolutionsbringsleading-edgelogicsynthesisandverificationproductstoFPGAandASICdesignersSynplicityIntroduction35FPGAProductLineOverviewFPGAProductLineOverviewSynplifyProTool•ChallengingDesigns•ComplexProjects•TheUltimateinFPGASynthesisSynplifyTool•Fast•EasytoUse•ExcellentResultsAmplifyPhysicalOptimizerPhysicalSynthesisforFPGAs•HighestCircuitPerformance•FastestTimingClosure•OptiontoSynplifyProIntroduction6FPGASynthesiswiththeSynplifyProToolFPGASynthesiswiththeSynplifyProTool»UltraFastuB.E.S.T.TMalgorithms»EasytoUseuLanguagesensitiveTextEditoruHDLAnalyst®tooluS.C.O.P.E.®»ExcellentResultsuTiming-drivenuDirectmappingtotechnology-specificprimitivesIntroductionMarketLeaderinFPGASynthesis47GettingHelpGettingHelp»OnlineHelpuSelectHelp-Help,or[F1]functionkeyfromtheSynplifyProUI»SynplifyProUserGuideuPdffilefoundinSynplifyProInstallDir/docs»SynplifyProReferenceGuideuPdffilefoundinSynplifyProInstallDir/docs»SynplicitySupportuSynplify®OnlineSupport[SOS]andSynplifyNewsgroup»»news://news.synplicity.com/Synplicity.SynplifyuSynplifyFirstLevelSupport»[e-mail]ortHotlineat(408)215-6000Introduction8HDLCodingforPerformanceHDLCodingforPerformance»Introduction»HDLCodingforPerformanceHDLCodingTechniquesforPerformance59OverviewOverview»DiscussvariousHDLcodingissuesthataffectperformanceuSharedExpressionsuShannonExpansionuOperandReorderinguPriorityEncoding»ParallelCaseuRAMInferencinguOthercodingissues»LatchGeneration»SensitivityListHDLCodingTechniquesforPerformance10CommonBooleanExpressionsCommonBooleanExpressions»DefinitionuShareidenticalboolean(sub-)expressions(&,|,…)»ProsandConsuSavesAreauDoneautomaticallyuGenerallyhaveminimaltimingimpactuSomesituationsrequiresourcecodechanges»manualreplication»WhentouseituSharecommonexpressionstosavearea(automatic)uManuallyreplicateexpressionstocontrolloading»Largenumberofloadswithinablackbox»ReduceloadingonacriticalpathHDLCodingTechniquesforPerformance611CommonBooleanExpressionsCommonBooleanExpressions»ExampleuDesigndetails»Goal:meetloadrestrictionof10»Designhastwoblackboxes,eachwith8loadsontheeninput»TheSynplifyProtooldoesnotknowaboutloadingwithintheblackboxes»OriginalDesignua_enandb_enwereshared,resultingin16loadsonen»FixedDesignuManuallyforcedthea_enandb_entoremainseparateuEachenablesignaldriveonlyoneblackbox(8loads)HDLCodingTechniquesforPerformance12CommonBooleanExpressionsCommonBooleanExpressionsmodulebb_load(a1,a2,b1,b2,opcode,clk,rst,a_out,b_out);inputclk,rst;input[3:0]opcode;input[7:0]a1,a2,b1,b2;output[7:0]a_out,b_out;reg[7:0]a1_reg,a2_reg,b1_reg,b2_reg;wire[3:0]a_opcode;wire[3:0]b_opcode;wirea_en;wireb_en;always@(posedgeclkornegedgerst)if(!rst)begina1_reg=8'h00;a2_reg=8'h00;b1_reg=8'h00;b2_reg=8'h00;endelsebegina1_reg=a1;a2_reg=a2;b1_reg=b1;b2_reg=b2;endassigna_opcode=opcode;assignb_opcode=opcode;assigna_en=(a_opcode==4'b1011)?1'b1:1'b0;assignb_en=(b_opcode==4'b1011)?1'b1:1'b0;function_abb_A(a1_reg,a2_reg,a_en,a_out);function_bbb_B(b1_reg,b2_reg,b_en,b_out);endmodulemodulefunction_a(in1,in2,en,out)/*synthesissyn_black_box*/;inputen;input[7:0]in1,in2;output[7:0]out;endmodulemodulefunction_b(in1,in2,en,out)/*synthesissyn_black_box*/;inputen;input[7:0]in1,in2;output[7:0]out;endmodulea_enbeingsharedbetweenfunction_aandfunction_b,causingloadonittobe(8+8)=16HDLCodingTechniquesforPerformance713CommonBooleanExpressionsCommonBooleanExpressionsmodulefunction_a(in1,in2,en,out)/*synthesissyn_black_box*/;inputen;input[7:0]in1,in2;output[7:0]out;endmodulemodulefunction_b(in1,in2,en,out)/*synthesissyn_black_box*/;inputen;input[7:0]in1,in2;output[7:0]out;endmodulemodulebb_load(a1,a2,b1,b2,opcode,clk,rst,a_out,b_out);inputclk,rst;input[3:0]opcode;input[7:0]a1,a2,b1,b2;output[7:0]a_out,b_out;reg[7:0]a1_reg,a2_reg,b1_reg,b2_reg;wire[3:0]a_opcode/*synthesissyn_keep=1*/;wire[3:0]b_opcode/*synthesissyn_keep=1*/;wirea_en;wireb_en;always@(posedgeclkornegedgerst)if(!rst)begina1_reg=8'h00;a2_reg=8'h00;b1_reg=8'h00;b2_reg=8'h00;endelsebegina1_reg=a1;a2_reg=a2;b1_reg=b1;b2_reg=b2;endassigna_opcode=opcode;assignb_opcode=opcode;assigna_en=(a_opcode==4'b1011)?1'b1:1'b0;assignb_en=(b_opcode==4'b1011)?1'b1:1'b0;function_abb_A(a1_reg,a2_reg,a_en,a_out);function_bbb_B(b1_reg,b2_reg,b_en,b_out);endmoduleApplyingsyn_keeponthesignalsa_opcodeandb_opcode,dividetheloadontheenablesignaltomeetthedesignrequirement.HDLCodingTechniquesforPerformance14ShannonExpansion