BSIM3v322手册英文版

BSIM3v3.3MOSFETModelUsers’ManualWeidongLiu,XiaodongJin,XuemeiXi,JamesChen,Min-ChieJeng,ZhihongLiu,YuhuaCheng,KaiChen,MansunChan,KelvinHui,JianhuiHuang,RobertTu,PingK.KoandChenmingHuDepartmentofElectricalEngineeringandComputerSciencesUniversityofCalifornia,Berkeley,CA94720Copyright©2005TheRegentsoftheUniversityofCaliforniaAllRightsReservedDevelopers:TheBSIM3v3.3.0MOSFETmodelisdevelopedby•Prof.ChenmingHu,UCBerkeley•Dr.XuemeiXi,UCBerkeley•MohanDunga,UCBerkeleyDevelopersofPreviousVersions:•Dr.MansunChan,USTHK•Dr.KaiChen,IBM•Dr.YuhuaCheng,Rockwell•Dr.JianhuiHuang,IntelCorp.•Dr.KelvinHui,LatticeSemiconductor•Dr.JamesChen,UCBerkeley•Dr.Min-ChieJeng,CadenceDesignSystems•Dr.Zhi-HongLiu,BTATechnologyInc.•Dr.RobertTu,AMD•Prof.PingK.Ko,UST,HongKong•Prof.ChenmingHu,UCBerkeleyWebSitestoVisit:BSIMwebsite:~bsim3CompactModelCouncilwebsite::Dr.Xuemei(Jane)Xi:[e-mail]:ThedevelopmentofBSIM3v3.3benefitedfromtheinputofmanyBSIM3users,especiallytheCompactModelCouncil(CMC)membercompanies.ThedeveloperswouldliketothankKeithGreen,TomVrotsos,DavidZweidingerandClaudeR.CirbaatTI,JoeWattsatIBM,ColinMcAndrewatMotorola,Min-ChieJeng,ZhihongLiuatCadence,WeidongLiuatSynopsys,PaulHumphriesatAnalogDevices,Shiuh-WuuLee,PaulPackan,Wei-KaiShihatIntel,JudyAnatAMD,MohamedAhmed,MohamedHassan,andMohamedSelimatMentorGraphics,PeterLeeatRenesas,TakahiroIizukaatNEC,SallyLiu,Ke-WeiSuatTSMC,DanielWan,JinShyongJanatUMCfortheirvaluableassistanceinidentifyingthedesirablemodificationsandtestingofthenewmodel.SpecialacknowledgmentgoestoDr.JosefWatts,chairofCMC,Dr.KeithGreen,formerChairmanoftheTechnicalIssueSubcommitteeofCMC;andBhaskarGadepally,BrittBrooks,formerchairsofCMC.TheBSIM3projectispartiallysupportedbySRC,CMCandRockwellIntern:ational.BSIM3v3.3ManualCopyright©2005UCBerkeley1TableofContentsCHAPTER1:Introduction1-11.1GeneralInformation1-11.1Backwardcompatibility1-21.2OrganizationofThisManual1-2CHAPTER2:Physics-BasedDerivationofI-VModel2-12.1Non-UniformDopingandSmallChannelEffectsonThresholdVoltage2-12.1.1VerticalNon-UniformDopingEffect2-32.1.2LateralNon-UniformDopingEffect2-52.1.3ShortChannelEffect2-72.1.4NarrowChannelEffect2-122.2MobilityModel2-152.3CarrierDriftVelocity2-172.4BulkChargeEffect2-182.5StrongInversionDrainCurrent(LinearRegime)2-192.5.1IntrinsicCase(Rds=0)2-192.5.2ExtrinsicCase(Rds0)2-212.6StrongInversionCurrentandOutputResistance(SaturationRegime)2-222.6.1ChannelLengthModulation(CLM)2-252.6.2Drain-InducedBarrierLowering(DIBL)2-262.6.3CurrentExpressionwithoutSubstrateCurrentInducedBodyEffect2-272.6.4CurrentExpressionwithSubstrateCurrentInducedBodyEffect2-282.7SubthresholdDrainCurrent2-302.8EffectiveChannelLengthandWidth2-312.9PolyGateDepletionEffect2-33CHAPTER3:UnifiedI-VModel3-13.1UnifiedChannelChargeDensityExpression3-13.2UnifiedMobilityExpression3-6BSIM3v3.3ManualCopyright©2005UCBerkeley23.3UnifiedLinearCurrentExpression3-73.3.1Intrinsiccase(Rds=0)3-73.3.2ExtrinsicCase(Rds0)3-93.4UnifiedVdsatExpression3-93.4.1Intrinsiccase(Rds=0)3-93.4.2ExtrinsicCase(Rds0)3-103.5UnifiedSaturationCurrentExpression3-113.6SingleCurrentExpressionforAllOperatingRegimesofVgsandVds3-123.7SubstrateCurrent3-153.8ANoteonVbs3-15CHAPTER4:CapacitanceModeling4-14.1GeneralDescriptionofCapacitanceModeling4-14.2GeometryDefinitionforC-VModeling4-24.3MethodologyforIntrinsicCapacitanceModeling4-44.3.1BasicFormulation4-44.3.2ShortChannelModel4-74.3.3SingleEquationFormulation4-94.4Charge-ThicknessCapacitanceModel4-144.5ExtrinsicCapacitance4-194.5.1FringingCapacitance4-194.5.2OverlapCapacitance4-19CHAPTER5:Non-QuasiStaticModel5-15.1BackgroundInformation5-15.2TheNQSModel5-15.3ModelFormulation5-25.3.1SPICEsub-circuitforNQSmodel5-35.3.2Relaxationtime5-45.3.3Terminalchargingcurrentandchargepartitioning5-55.3.4Derivationofnodalconductances5-7BSIM3v3.3ManualCopyright©2005UCBerkeley3CHAPTER6:ParameterExtraction6-16.1Optimizationstrategy6-16.2ExtractionStrategies6-26.3ExtractionProcedure6-26.3.1ParameterExtractionRequirements6-26.3.2Optimization6-46.3.3ExtractionRoutine6-66.4NotesonParameterExtraction6-146.4.1ParameterswithSpecialNotes6-146.4.2ExplanationofNotes6-15CHAPTER7:BenchmarkTestResults7-17.1BenchmarkTestTypes7-17.2BenchmarkTestResults7-2CHAPTER8:NoiseModeling8-18.1FlickerNoise8-18.1.1Parameters8-18.1.2Formulations8-28.2ChannelThermalNoise8-48.3NoiseModelFlag8-5CHAPTER9:MOSDiodeModeling9-19.1DiodeIVModel9-19.1.1ModelingtheS/BDiode9-19.1.2ModelingtheD/BDiode9-39.2MOSDiodeCapacitanceModel9-59.2.1S/BJunctionCapacitance9-59.2.2D/BJunctionCapacitance9-79.2.3TemperatureDependenceofJunctionCapacitance9-10BSIM3v3.3ManualCopyright©2005UCBerkeley49.2.4JunctionCapacitanceParameters9-11APPENDIXA:ParameterListA-1A.1ModelControlParametersA-1A.2DCParametersA-1A.3C-VModelParametersA-6A.4NQSParametersA-8A.5dWanddLParametersA-9A.6TemperatureParametersA-10A.7FlickerNoiseModelParametersA-12A.8ProcessParametersA-13A.9GeometryRangeParametersA-14A.10ModelParameterNotesA-14APPENDIXB:EquationListB-