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1BLDCMotorSpeedEstimationUsingPDCTimerModule1SpeedCalculationofBLDC1.1SummaryofBLDCSincecurrentBLDChassubstitutedtheelectricalcommutatorforthemechanicalone,iteliminatesthedisadvantagesofnoise,spark,electromagneticdisturbance,shortlifetime,etc.NowBLDCisprovidedwithadvantagesofsimplestructure,dependableoperationandeasymaintenanceasACmotordoes,aswellasadvantagesofhighefficient,noexcitationcostandfunctionalspeedregulationastraditionalDCmotordoes.Soitiswidelyusedinvariousfieldsofindustrialcontrolnow.1.2PDCModuleIntroductionSPMC75F2413Aprovidestwochannelsof16bitPDC(PhaseDetectionControl,PDC)timersusedforcapturefunctionandPWMoperation.ItalsosupportspositiondetectionfeaturesforBrushless-DCmotorapplication.ThePDCtimersareverysuitableforbothmechanicalspeedcalculation,withACIandBLDCmotorincluded,andphasecommutationforchangingcurrentconductionaccordingtopositioninformation.Figure1-1showstheblockdiagramofentirePDCtimers,channel0andchannel1.FordetailsofPDCtimer’sspecification,pleaserefertoTable1-1.Table1-1PDCTimerFunctionPDCTimer0PDCTimer1ClocksourcesInternalclock:FCK/1,FCK/4,FCK/16,FCK/64,FCK/256,FCK/1024Externalclock:TCLKA,TCLKBInternalclock:FCK/1,FCK/4,FCK/16,FCK/64,FCK/256,FCK/1024Externalclock:TCLKA,TCLKBIOpinsTIO0A,TIO0B,TIO0CTIO1A,TIO1B,TIO1CTimergeneralregisterP_TMR0_TGRA,P_TMR0_TGRB,P_TMR0_TGRCP_TMR1_TGRA,P_TMR1_TGRB,P_TMR1_TGRCTimerbufferregisterP_TMR0_TBRA,P_TMR0_TBRB,P_TMR0_TBRCP_TMR1_TBRA,P_TMR1_TBRB,P_TMR1_TBRCTimerperiodandP_TMR0_TPR,P_TMR1_TPR,2counterregisterP_TMR0_TCNTP_TMR1_TCNTCapturesampleclockInternalclock:FCK/1,FCK/2,FCK/4,FCK/8Internalclock:FCK/1,FCK/2,FCK/4,FCK/8CountingedgeCountonrising,falling,bothedgeCountonrising,falling,bothedgeCounterclearsourceClearedonP_TMR0_TGRA,P_TMR0_TGRB,P_TMR0_TGRCcaptureinput.ClearedonP_POS0_DectDatapositiondetectiondatachanges.ClearedonP_TMR0_TPRcomparematches.ClearedonP_TMR1_TGRA,P_TMR1_TGRB,P_TMR1_TGRCcaptureinput.ClearedonP_POS1_DectDatapositiondetectiondatachanges.ClearedonP_TMR1_TPRcomparematches.InputcapturefunctionYesYesPWMcomparematchoutputfunction1outputYesYes0outputYesYesOutputHoldYesYesEdge-alignedPWMYesYesCenter-alignedPWMYesYesPhasecountingmodeYes,phaseinputsareTCLKA/TCLKBYes,phaseinputsareTCLKC/TCLKDTimerbufferoperationYesYesADconvertstarttriggerP_TMR0_TGRAcomparematchP_TMR1_TGRAcomparematchInterruptsourcesTimer0TPRinterruptTimer0TGRAinterruptTimer0TGRBinterruptTimer0TGRCinterruptTimer0PDCinterruptTimer0overflowinterruptTimer0underflowinterruptTimer1TPRinterruptTimer1TGRAinterruptTimer1TGRBinterruptTimer1TGRCinterruptTimer1PDCinterruptTimer1overflowinterruptTimer1underflowinterrupt3Figure1-1PDCTimersBlockDiagram1.3PDCOperationThisnotemainlydepictsPDCapplicationinmotorspeedmeasurement.FordetailedPDCintroduction,pleasereferto“SPMC75F2413AProgrammingGuide”authoredbySunplus.PDCmodulehasfourtypesofregisterstoperformspeedmeasurement:TimercontrolregisterP_TMRx_Ctrl(x=0,1),positiondetectioncontrolregisterP_POSx_DectCtrl(x=0,1),inputoutputcontrolregisterP_TMRx_IOCtrl(x=0,1),andtimerinterruptenableregisterP_TMRx_INT(x=0,1).Where,P_TMRx_CtrlandP_POSx_DectCtrlareintroducedindetail.1.31InputOutputControlRegisterP_TMRx_Ctrl(x=0,1)B15B14B13B12B11B10B9B8R/WR/WR/WR/WR/WR/WR/WR/W000000004SPCKMODECLEGSB7B6B5B4B3B2B1B0R/WR/WR/WR/WR/WR/WR/WR/W00000000SPCKMODECLEGSBit15:14SPCK:Captureinputsampleclockselect.Thesebitsselectthecaptureinputsampleclock.Captureinputwillbesampledwithsampleclock.Pulsesshorterthanfoursampleclockswillbeconsideredinvalid,andwillbeignored.00=FCK/101=FCK/210=FCK/411=FCK/8Bit13:10MODE:Modesselect.Thesebitsareusedtoselectthetimeroperationmodes.0000=Normaloperation(continuouscounterupcounting)0100=Phasecountingmode10101=Phasecountingmode20110=Phasecountingmode30111=Phasecountingmode41x0x=Edge-alignedPWMmode(continuouscounterupcounting,PWMoutput)1x1x=Center-alignedPWMmode(continuouscounterup/downcounting,PWMoutput)Bit9:8CLEGS:Counterclearedgeselect.Thesebitsselectthecounterclearingedgewhentheclearingsourceisininputcapturemode.00=donotclear01=risingedge10=fallingedge11=bothedgeBit7:5CCLS:Counterclearsourceselect.ThesebitsselecttheTCNTcounterclearingsource.5000=TCNTclearingdisabled001=TCNTclearedbyP_TMRx_TGRA(x=0,1)captureinput010=TCNTclearedbyP_TMRx_TGRB(x=0,1)captureinput011=TCNTclearedbyP_TMRx_TGRC(x=0,1)captureinput100=TCNTclearedbyeveryP_POSx_DectData(x=0,1)change6times101=TCNTclearedbyeveryP_POSx_DectData(x=0,1)change3times110=TCNTclearedbyP_POSx_DectData(x=0,1)positiondetectiondatachange111=TCNTclearedbyP_TMRx_TPR(x=0,1)comparematchBit4:3CKEGS:Clockedgeselect,Thesebitsselecttheinputclockedge.Whentheinputclockiscountedusingbothedges,theinputclockperiodishalved.WhenFCK/1isselectedascounterclock,counterwillcountatrisingedgeifcountatbothedgesisselected.00=Countatrisingedge01=Countatfallingedge1X=CountatbothedgesBit2:0TMRPS:Timerpre-scalarselect.ThesebitsselecttheTCNTcounterclocksource.Itcanbeselectedindependentlyforeachchannel.000=CountsonFCK/1001=CountsonFCK/4010=CountsonFCK/16011=CountsonFCK/64100=CountsonFCK/256101=CountsonFCK/1024110=CountsonTCLKApini