常见面试笔试题-verilog程序库

加减法moduleaddsub(input[7:0]dataa,input[7:0]datab,inputadd_sub,//ifthisis1,add;elsesubtractinputclk,outputreg[8:0]result);always@(posedgeclk)beginif(add_sub)result=dataa+datab;//orassign{cout,sum}=dataa+datab;elseresult=dataa-datab;endendmodule四位的全加法器.moduleadd4(cout,sum,a,b,cin)input[3:0]a,b;inputcin;output[3:0]sum;outputcout;assign{cout,sum}=a+b+cin;endmodule补码不仅可以执行正值和负值转换，其实补码存在的意义，就是避免计算机去做减法的操作。1101-3补+1000801015假设-3+8，只要将-3转为补码形式，亦即0011=1101，然后和8，亦即1000相加就会得到5，亦即0101。至于溢出的最高位可以无视掉。乘法器modulemult(outcome,a,b);parameterSIZE=8;input[SIZE:1]a,b;outputreg[2*SIZE:1]outcome;integeri;always@(aorb)beginoutcome=0;for(i=0,i=SIZE;i=i+1)if(b[i])outcome=outcome+(a(i-1));endendmodule另一种乘法器。在初始化之际，取乘数和被乘数的正负关系，然后取被乘数和乘数的正值。输出结果根据正负关系取得。elseif(Start_Sig)case(i)0:beginisNeg=Multiplicand[7]^Multiplier[7];Mcand=Multiplicand[7]?(~Multiplicand+1'b1):Multiplicand;Mer=Multiplier[7]?(~Multiplier+1'b1):Multiplier;Temp=16'd0;i=i+1'b1;end1://Multiplingif(Mer==0)i=i+1'b1;elsebeginTemp=Temp+Mcand;Mer=Mer-1'b1;end2:beginisDone=1'b1;i=i+1'b1;end3:beginisDone=1'b0;i=2'd0;endendcaseassignDone_Sig=isDone;assignProduct=isNeg?(~Temp+1'b1):Temp;endmodulebooth乘法器modulebooth_multiplier_module(inputCLK,inputRSTn,inputStart_Sig,input[7:0]A,input[7:0]B,outputDone_Sig,output[15:0]Product,output[7:0]SQ_a,output[7:0]SQ_s,output[16:0]SQ_p);reg[3:0]i;reg[7:0]a;//resultofAreg[7:0]s;//reverseresultofAreg[16:0]p;//p空间，16+1位reg[3:0]X;//指示n次循环regisDone;always@(posedgeCLKornegedgeRSTn)if(!RSTn)begini=4'd0;a=8'd0;s=8'd0;p=17'd0;X=4'd0;isDone=1'b0;endelseif(Start_Sig)case(i)0:begina=A;s=(~A+1'b1);p={8'd0,B,1'b0};i=i+1'b1;end1:if(X==8)beginX=4'd0;i=i+4'd2;endelseif(p[1:0]==2'b01)beginp={p[16:9]+a,p[8:0]};i=i+1'b1;endelseif(p[1:0]==2'b10)beginp={p[16:9]+s,p[8:0]};i=i+1'b1;endelsei=i+1'b1;//00和11，无操作2:beginp={p[16],p[16:1]};X=X+1'b1;i=i-1'b1;end//右移，最高位补0or1.3:beginisDone=1'b1;i=i+1'b1;end4:beginisDone=1'b0;i=4'd0;endendcaseassignDone_Sig=isDone;assignProduct=p[16:1];endmodule除法器moduledivider_module(inputCLK,inputRSTn,inputStart_Sig,input[7:0]Dividend,input[7:0]Divisor,outputDone_Sig,output[7:0]Quotient,output[7:0]Reminder,);reg[3:0]i;reg[7:0]Dend;reg[7:0]Dsor;reg[7:0]Q;reg[7:0]R;regisNeg;regisDone;always@(posedgeCLKornegedgeRSTn)if(!RSTn)begini=4'd0;Dend=8'd0;Dsor=8'd0;Q=8'd0;isNeg=1'b0;isDone=1'b0;endelseif(Start_Sig)case(i)0:beginDend=Dividend[7]?~Dividend+1'b1:Dividend;Dsor=Divisor[7]?Divisor:(~Divisor+1'b1);isNeg=Dividend[7]^Divisor[7];i=i+1'b1;end1:if(DivisorDend)beginQ=isNeg?(~Q+1'b1):Q;i=i+1'b1;endelsebeginDend=Dend+Dsor;Q=Q+1'b1;end2:beginisDone=1'b1;i=i+1'b1;end3:beginisDone=1'b0;i=4'd0;endendcaseassignDone_Sig=isDone;assignQuotient=Q;assignReminder=Dend;endmodule除法器2modulediv(a,b,clk,result,yu)input[3:0]a,b;outputreg[3:0]result,yu;inputclk;reg[1:0]state;reg[3:0]m,n;parameterS0=2'b00,S1=2'b01,S2=2'b10;always@(posedgeclk)begincase(state)S0:beginif(ab)beginn=a-b;m=4'b0001;state=S1;endelsebeginm=4'b0000;n=a;state=S2;endendS1:beginif(n=b)beginm=m+1;n=n-b;state=S1;endelsebeginstate=S2;endendS2:beginresult=m;yu=n;state=S0;enddefule:state=S0;endcaseendendmodule13、一个可预置初值的7进制循环计数器①verilogmodulecount(clk,reset,load,date,out);inputload,clk,reset;input[3:0]date;outputreg[3:0]out;parameterWIDTH=4'd7;always@(clkorreset)beginif(reset)out=4'd0;elseif(load)out=date;elseif(out==WIDTH-1)out=4'd0;elseout=out+1;endendmoduleJohnson计数器约翰逊(Johnson)计数器又称扭环计数器,是一种用n位触发器来表示2n个状态的计数器。它与环形计数器不同,后者用n位触发器仅可表示n个状态。n位二进制计数器(n为触发器的个数)有2^n个状态。若以四位二进制计数器为例,它可表示16个状态。“0000-1000-1100-1110-1111-0111-0011-0001-0000-1000……”moduleJohnson(inputclk,inputclr,outputreg[N-1:0]q);always@(posedgeclkornegedgeclr)if(!clr)q={N{1’b0}}elseif(!q[0])q={1’b1,q[N-1:1]};elseq={1’b0,q[N-1]:1}];endmodule任意分频，占空比不为50%always(clk)beginif(count==x-1)count=0;elsecount=count+1;endassignclkout=count[y]//y一般用count的最高位偶数分频(8分频，占空比50%)（计数至n-1，翻转）modulecount5(reset,clk,out)inputclk,reset;outputout;reg[1:0]count;always@(clk)if(reset)begincount=0;out=0;endelseif(count==3)begincount=0;out=!out:endelsecount=count+1;endmodule奇数分频电路（占空比50%）。modulecount5(reset,clk,out)inputclk,reset;outputout;reg[2:0]m,n;regcount1;regcount2;always@(posedgeclk)beginif(reset)beginm=0;count1=0;endelsebeginif(m==4)m=0;elsem=m+1;//“4”为分频数NUM-1，NUM=5if(m2)count1=1;elsecount1=0;endendalways@(negedgeclk)beginif(reset)beginn=0;count2=0;endelsebeginif(n==4)n=0;elsen=n+1;if(n2)count2=1;elsecount2=0;endendassignout=count1|count2;半整数分频modulefdiv5_5(clkin,clr,clkout)inputclkin,clr;outputregclkout;regclk1;wireclk2;integercount;xorxor1(clk2,clkin,clk1)always@(posedgeclkoutornegedgeclr)beginif(~clr)beginclk1=1’b0;endelseclk1=~clk1;endalways@(posedgeclk2ornegedgeclr)beginif(~clr)begincount=0;clkout=1’b0;endelseif(count==5)begincount=0;clkout=1’b1;endelsebegincount=count+1;clkout=1’b0;endendendmodule小数分频N=M/P.N为分配比，M为分频器输入脉冲数，P为分频器输出脉冲数。N=(8×9+9×1)/（9+1）=8.1先做9次8分频再做1次9分频。modulefdiv8_1(clkin,rst,clkout)inputclkin,rst;outputregclkout;reg[3:0]cnt1,cnt2