xapp524-serial-lvds-adc-interface

XAPP524(v1.1)November20,2012©Copyright2012Xilinx,Inc.Xilinx,theXilinxlogo,Artix,ISE,Kintex,Spartan,Virtex,Vivado,Zynq,andotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountries.Allothertrademarksarethepropertyoftheirrespectiveowners.SummaryThisapplicationnotedescribesamethodofutilizingdedicatedSelectIO™technologydeserializercomponents(ISERDESE2primitives)in7seriesFPGAstointerfacewithanalog-to-digitalconverters(ADC)withserial,low-voltage,differentialsignalling(LVDS)outputs.TheassociatedreferencedesignillustratesabasicLVDSinterfaceconnectingaKintex™-7FPGAtoanADCwithhigh-speed,serialLVDSoutputs.IntroductionThehigh-speedADCsusedtodayhavearesolutionof12,14,or16bitswithpossiblemultipleconvertersinasinglepackage.Eachoftheconvertersinthepackagecanbeusedinstandalonemodeorconvertersinthepackagecanbecombinedandusedinaninterleavedmodetodoubleorquadrupletheconversion(sample)speed.Inbothstandalonemodeorinterleavedmode,oneortwophysicalserialoutputscanbeusedasaconnectiontotheinterfacingdevice.Onesetofdifferentialoutputsiscalledadatalane.Usingonedatalanemeansthattheconverterisusedin1-wiremodeandtwodatalanesarecalled2-wiremode.Foreverypossibledataoutputcombinationthereisalwaysonehigh-speedbitclockandonesamplerateframeclockavailable.The1-wiremodeisusedinSDRandDDRconfigurationsand2-wiremodeusesonlyDDRmode.The1-wiremodekeepstheamountofinterconnectionslowandusesnormallyonedatalaneperconverterinapackage.Secondly,the1-wiremodecanbeusedtooutputdataofoneortwoconvertersinaninterleavedformat.Exampleoftwoconvertersusinga1-wiresetup:�Oneconverteroutputsdataontherisingedgeofthebitclockandthesecondconverterusesthefallingclockedge.�Thisimmediatelydoublesthebitclockrateandisthereforenotmuchused.The2-wiremodedoublestheamountofconnectionsbetweentheADCandinterfacingdevice,buthasthegreatadvantagetodividethebitclockbytwo.Asingleconvertercandoublethesampleclockratewhilethebitclockdoesn'tchangefrequencyoraconvertercankeepitssampleclockratewhilethebitclockgetsdividedbytwo.Inbothcasesthedataisoutputininterleavedformatovertwodatalanes.TheFPGA’sSelectIOtechnologydeserializercomponentsareconfiguredasISERDESE2primitives.TwoISERDESE2sinsingledatarate(SDR)modeareusedtocaptureadoubledatarate(DDR)signal.OneISERDESE2isclockedattherisingedgeandthesecondatthefallingedgeofthebitclock(CLK).Thismethodallowscapturingupto16bits,eachISERDESE2cancapture8bits.ApplicationNote:7SeriesFPGAsXAPP524(v1.1)November20,2012SerialLVDSHigh-SpeedADCInterfaceAuthor:MarcDefossezFPGAResourcesXAPP524(v1.1)November20,2012(HR)andhigh-performance(HP)I/Obanks.ImportantforADCinterfacesisthatISERDESE2(Figure1)andIDELAYE2(Figure2)componentsareavailableinbothHRandHPbanks.TheHRI/ObankssupportLVDS2.5VI/OandHPbankssupportLVDSat1.8V(VCCOlevel).FordetailsabouttheseHRandHPI/ObanksandtheISERDESE2andIDELAYE2components,seeUG471,7SeriesFPGAsSelectIOResourcesUserGuide.ADCLVDSInterfaceManyADCsuseaserializedLVDSinterfacetoprovidedigitaldataoveroneortwoLVDSchannelsperADCinthecomponentpackagetotheFPGA.Figure3showstheanaloginputsignalalongwiththeinput,bit,andframeclocks.SampleNoftheanalogsignalisconvertedtodigitalformatandpresentedattheADCoutputsafteralatencyperiod.Theanalogsignalisconvertedintoadigital,serialdatastreamwith12-bitADCresolutionthatisprovidedtogetherwithahigh-speedbitclockandasyncorframeclock.X-RefTarget-Figure1Figure1:ISERDESE2X-RefTarget-Figure2Figure2:IDELAYE2INTERFACE_TYPE:string:=NETWORKING;SERDES_MODE:string:=MASTER;DATA_WIDTH:integer:=8;DATA_RATE:string:=DDR”;OFB_USED:string:=FALSE;IOBDELAY:string:=NONE;NUM_CE:integer:=2;DYN_CLKDIV_INV_EN:string:=FALSE;DYN_CLK_INV_EN:string:=FALSE;INIT_Q1:bit:='0';INIT_Q2:bit:='0';INIT_Q3:bit:='0';INIT_Q4:bit:='0';SRVAL_Q1:bit:='0';SRVAL_Q2:bit:='0';SRVAL_Q3:bit:='0';SRVAL_Q4:bit:='0'ISERDESE2SHIFTIN1SHIFTIN2OFBDDDLYCE1CE2RSTBITSLIPCLKCLKBCLKDIVCLKDIVPDYNCLKDIVSELDYNCLKSELOCLKOCLKBOQ1Q2Q3Q4Q5Q6Q7Q8SHIFTOUT1SHIFTOUT2X524_01_012912CINVCTRL_SEL:string:=“FALSE”;DELAY_SRC:string:=‘IDATAIN’;HIGH_PERFORMANCE_MODE:string;=“FALSE’;IDELAY_TYPE:string:=”FIXED”;IDELAY_VALUE:integer:=0;PIPE_SEL:string:=“FALSE”;REFCLK_FREQUENCY:real:=200.0;SIGNAL_PATTERN:string:=“DATA”ISERDESE2DATAINIDATAINCNTVALUEIN[4:0]CEINCLDLDPIPEENREGRSCCINVCTRLCNTVALUEOUT[4:0]DATAOUTX524_02_012912ADCLVDSInterfaceXAPP524(v1.1)November20,2012(FCLK)isadigitizedandphase-shiftedversionoftheADCsampleclock.FCLKisphasealignedwiththeserialdata,andalldatabitsofasamplefitintooneframeclockperiod.Thehigh-speedbitclock(DCLK)ispresentedasa90°phase-shiftedsignaltothedataandFCLK.In1-wiremode,thereareasmanydatachannelsasconvertersinthepackage.In2-wiremode,thedataissplitovertwodatachannelsperconverter.ThefrequencyofDCLKisdeterminedbytheADC'sresolutionandsamplerate.Therefore,anADCprovidesoneortwodatalanesperconverterinthepackage,butonlyoneDCLKandoneFCLK.ThemaximumspeedoftheLVDSI/OissetbythemaximumpossiblespeedthatDCLKcantoggletheflip-flopsintheFPGAlogicorintheISERDESE2.Therefore,th