uC-OS-内核在基于FPGA的CPU上的移植

uC/OS2IIFPGACPU1,1,2,1(1.,100084;2.,100084):FPGA(fieldprogrammablegatearry)CPUMiniArm,uC/OS2IIMiniArm,,,FPGACPU:FPGA;CPU;uC/OS2II;:TP311:B:100224956(2010)0420087204TransplantinguC/OS2IIkerneltoFPGA2basedCPUMiniArmLiShanshan1,LiYaoqiang1,LiuJinghan2,TangZhizhong1(1.LaboratoryforComputerEducation,TsinghuaUniversity,Beijing100084,China;2.TheFundamentalIndustrialTrainingCenter,TsinghuaUniversity,Beijing100084,China)Abstract:ThisarticleintroducesFPGA2basedCPUcalledMiniArm,mainlyonitsinstructionset,structureanddetailedimplementation;discussesthekeytechnologyoftransplantinguC/OS2IIkerneltoMiniArm,andthedetailedprocessoftheimplementisintroduced;analyzesthetestmethodandtheresultofthetransplan2ting;andfinallysummarizesthegeneralmethodsoftransplantingoperatingsystemtoFPGA2basedCPU.Keywords:FPGA;CPU;uC/OS2II;transplantation:2009204222:(60173010):(1979),,,,,:.,FPGA(fieldprogrammablegatear2ry)CPU,,CPU,CPU,,FPGACPU,FPGACPUMiniArm,,uC/OS2II,,,1MiniArmCPUMiniArmFPGA32CPU[1],FPGACyclonIIEP2C20Q240C8CPU5;Cache;Arm7TDMI[2],;USR,IRQ,SVC,SYS41.1MiniArmuC/OS2II,uC/OS2II,Arm7[3],11MiniArm1mov8and,sub2bl,bx/6ldr,ldrb,ldrh2ldm,stm2mrs,msr1nop3lsl,lsr,asrISSN1002-4956CN11-2034/TExperimentalTechnologyandManagement27420104Vol.27No.4Apr.20101.2CPU5[4],Cache,1,MiniArm:5Arm7TDMI1MiniArm1.31.3.1(1)IF,IPI2Cache(2)ID,1932(3)EXE,ALU8,(4)MEM(5)WB1.3.2/Bubble/StallUnit,:,IP:(1)Cache,IP,,,,;(2)Cache,;(3),;(4)ldr,IP,,(5)ldr,3,1.3.3/I2Cache/D2CacheCache,4:ST_RESET0(),ST_RESET(),ST_NORMAL(),ST_REPLACING(Cache)Cache,:ST_RESET0(),ST_RESET(),ST_NORMAL(),ST_WRITEBACK1(Cache1),ST_WRITEBACK2(Cache2),ST_REPLACING(Cache)2uC/OS2II2.1uC/OS2IIuC/OS2II,,,,64,56;,,,[5],ArmCPUuC/OS2IIwindowsArmDevelopmentSuiteAXD,,uC/OS2,,RomFPGA;,15kB,FPGA,uC/OS2II,uC/OS2IIintelXScalePX255[627]2.2uC/OS2IIArmDeveloperSuitev1.2(ADS),CodeWarrior;ARMeXtendedDebugger(AXD)ADSuC/OS2IIAXD,ModelSim,uC/OS2II3,:(1)uC/OS2II,MiniArm,[6](2)CPUMiniArmUSR,SVC,SYS,IRQ,main.sUND,ABT,FIQ88(3)MiniArm,uC/OS2II,MiniArmmain.incRom,Ram,:ROM_BaseEQU0x00000000;ROMROM_SizeEQU0x00004000;RAMRAM_BaseEQU0x00004000;Globe_Variable_SizeEQU1531024STACK_SIZEEQU102431RAM_Source_BaseEQURAM_Base+Globe_Variable_Size+STACK_SIZESTACK_LOCATIONEQURAM_Source_BaseSTACK_LOCATION=RAM_Base+Globe_Variable_Size+STACK_SIZE=0x8000,SVCSTACK_LOCATION23STACK_SIZE=0x7800Ram:ER_data_plus_bss0x000040003,3.1(1)uC/OS2II,,CEntry.c(),voidtask2(void3pd){for(;;){}}main,OS2Start,,task2;r9RAM0x4000,SVCmain,0x77f8,0ADS,uCOS_II_DeadCircle.bin,15kAXD,CPUARM7TDMI,uCOS_II_DeadCircle.binTask2cpsr0x00000013,svcR13_svc0x77F8.(2)ModelSimModelsimMiniArm,22R13,R14,R16,R17,R18,R19R13_usr,R14_usr,R13_svc,R14_svc,R13_irq,R14_irqIP0x32dc,[0xeafffffe],btask2,,ID,;IP0x32e0,[0xe3a00005],ID[0xeafffffe]btask2,task2,CPSR0x00000013,svc,svc,ModelSimTask2,,,OStaskstkInit,OSTaskCreate,OSStart,uC/OS2IIMiniArm3.23.2.12,,2voidYouTask(void3pd){for(;;){98,:uC/OS2IIFPGACPUif(timecount==0)OSTaskResume(0);timecount--;}}voidMyTask(void3pd){OSTaskCreate(YouTask,(void3)0,&YouTaskStk[TASK_STK_SIZE-1],2);for(;;){if(timecount==3)OSTaskSuspend(OS_PRIO_SELF);timecount++;};},AXD,YouTaskMyTask3.2.2ModelSimModelsimMiniArmuCOS_II_Dispatcher.hex,33MiniArm707920ns1MyTask,,732600ns1YouTask,,742180nsMyTask,2,,OSTaskSus2pend,OSTaskResume,OS_Sched,MiniArm,3.3,AlteraFPGAEP2C20,MiniArmFPGA,uC/OS2IIRAM,,,4,;,MiniArm,uC/OS2IIFPGA,,,5FPGACPUMiniArm,uC/os2IIMiniArm,CPU,CPU,,;,CPU,,;,,,;CPUFPGA(References):[1],,.FPGACPU[J].,2005(14):982100.[2].ARM[M].:,2003.[3].ARM[M].:,2006.[4]JohnL.Hennessy,DavidA.Patterson.[M].4.,.:,2007.[5]LabrosseJJ.uC/OS2II22[M].,.:,2003.[6],,.IntelXScale[M].:,2004.[7]RajKaml.[M].,.:,2005.09