计算机组成与设计-第五版答案-Chapter05-Solution

Solutions5Chapter5SolutionsS-35.15.1.145.1.2I,J5.1.3A[I][J]5.1.435968800/4288/48000/45.1.5I,J5.1.6A(J,I)5.25.2.1WordAddressBinaryAddressTagIndexHit/Miss30000001103M18010110100114M4300101011211M20000001002M191101111111115M880101100058M190101111101114M1400001110014M18110110101115M4400101100212M186101110101110M253111111011513M5.2.2WordAddressBinaryAddressTagIndexHit/Miss30000001101M18010110100112M430010101125M20000001001H19110111111117M880101100054M19010111110117H140000111007M18110110101112H440010110026M18610111010115M25311111101156MS-4Chapter5Solutions5.2.3Cache1Cache2Cache3WordAddressBinaryAddressTagindexhit/missindexhit/missindexhit/miss30000001103M1M0M18010110100224M2M1M430010101153M1M0M20000001002M1M0M19110111111237M3M1M8801011000110M0M0M19010111110236M3H1H140000111016M3M1M18110110101225M2H1M440010110054M2M1M18610111010232M1M0M25311111101315M2M1MCache1missrate100%Cache1totalcycles1225122324Cache2missrate10/1283%Cache2totalcycles1025123286Cache3missrate11/1292%Cache3totalcycles1125125335Cache2providesthebestperformance.5.2.4Firstwemustcomputethenumberofcacheblocksintheinitialcacheconfiguration.Forthis,wedivide32KiBby4(forthenumberofbytesperword)andagainby2(forthenumberofwordsperblock).Thisgivesus4096blocksandaresultingindexfieldwidthof12bits.Wealsohaveawordoffsetsizeof1bitandabyteoffsetsizeof2bits.Thisgivesusatagfieldsizeof321517bits.Thesetagbits,alongwithonevalidbitperblock,willrequire18409673728bitsor9216bytes.Thetotalcachesizeisthus92163276841984bytes.Thetotalcachesizecanbegeneralizedtototalsizedatasize(validbitsizetagsize)blockstotalsize41984datasizeblocksblocksizewordsizewordsize4tagsize32log2(blocks)log2(blocksize)log2(wordsize)validbitsize1Chapter5SolutionsS-5Increasingfrom2-wordblocksto16-wordblockswillreducethetagsizefrom17bitsto14bits.Inordertodeterminethenumberofblocks,wesolvetheinequality:4198464blocks15blocksSolvingthisinequalitygivesus531blocks,androundingtothenextpoweroftwogivesusa1024-blockcache.Thelargerblocksizemayrequireanincreasedhittimeandanincreasedmisspenaltythantheoriginalcache.Thefewernumberofblocksmaycauseahigherconflictmissratethantheoriginalcache.5.2.5Associativecachesaredesignedtoreducetherateofconflictmisses.Assuch,asequenceofreadrequestswiththesame12-bitindexfieldbutadifferenttagfieldwillgeneratemanymisses.Forthecachedescribedabove,thesequence0,32768,0,32768,0,32768,…,wouldmissoneveryaccess,whilea2-waysetassociatecachewithLRUreplacement,evenonewithasignificantlysmalleroverallcapacity,wouldhitoneveryaccessafterthefirsttwo.5.2.6Yes,itispossibletousethisfunctiontoindexthecache.However,informationaboutthefivebitsislostbecausethebitsareXOR’d,soyoumustincludemoretagbitstoidentifytheaddressinthecache.5.35.3.185.3.2325.3.31(22/8/32)1.0865.3.435.3.50.255.3.6Index,tag,data0000012,00012,mem[1024]0000012,00112,mem[16]0010112,00002,mem[176]0010002,00102,mem[2176]0011102,00002,mem[224]0010102,00002,mem[160]S-6Chapter5Solutions5.45.4.1TheL1cachehasalowwritemisspenaltywhiletheL2cachehasahighwritemisspenalty.AwritebufferbetweentheL1andL2cachewouldhidethewritemisslatencyoftheL2cache.TheL2cachewouldbenefitfromwritebufferswhenreplacingadirtyblock,sincethenewblockwouldbereadinbeforethedirtyblockisphysicallywrittentomemory.5.4.2OnanL1writemiss,thewordiswrittendirectlytoL2withoutbringingitsblockintotheL1cache.IfthisresultsinanL2miss,itsblockmustbebroughtintotheL2cache,possiblyreplacingadirtyblockwhichmustfirstbewrittentomemory.5.4.3AfteranL1writemiss,theblockwillresideinL2butnotinL1.AsubsequentreadmissonthesameblockwillrequirethattheblockinL2bewrittenbacktomemory,transferredtoL1,andinvalidatedinL2.5.4.4Oneinfourinstructionsisadataread,oneinteninstructionsisadatawrite.ForaCPIof2,thereare0.5instructionaccessespercycle,12.5%ofcycleswillrequireadataread,and5%ofcycleswillrequireadatawrite.Theinstructionbandwidthisthus(0.003064)0.50.096bytes/cycle.Thedatareadbandwidthisthus0.02(0.130.050)640.23bytes/cycle.Thetotalreadbandwidthrequirementis0.33bytes/cycle.Thedatawritebandwidthrequirementis0.0540.2bytes/cycle.5.4.5Theinstructionanddatareadbandwidthrequirementisthesameasin5.4.4.Thedatawritebandwidthrequirementbecomes0.020.30(0.130.050)640.069bytes/cycle.5.4.6ForCPI1.5theinstructionthroughputbecomes1/1.50.67instructionspercycle.Thedatareadfrequencybecomes0.25/1.50.17andthewritefrequencybecomes0.10/1.50.067.Theinstructionbandwidthis(0.003064)0.670.13bytes/cycle.Forthewrite-throughcache,thedatareadbandwidthis0.02(0.170.067)640.22bytes/cycle.Thetotalreadbandwidthis0.35bytes/cycle.Thedatawritebandwidthis0.06740.27bytes/cycle.Forthewrite-backcache,thedatawritebandwidthbecomes0.020.30(0.170.067)640.091bytes/cycle.Address041613223216010243014031001802180LineID001814100191118Hit/missMHMMMMMHHMMMReplaceNNNNNNYNNYNYChapter5SolutionsS-75.55.5.1Assumingtheaddressesgivenasbyteaddresses,eachgroupof16accesseswillmaptothesame32-byteblocksothecachewillhaveamissrateof1/16.Allmissesarecompulsorymisses.Themissrateisnotsensitivetot