Modeling-with-Verilog-A[1]

AllRightReservedIntroductionJiaoChaoTsinghuaUniversityFeb.2006AllRightReserved•Verilog-Aoverview•Asimpleexample•Verilog-Asolution•Howtodescribethesystemstructure?•Howtodescribethecomponentbehavior?•UseVerilog-AinCadenceAllRightReserved•AnIEEEstandardanaloghardwaredescriptionlanguage.Designedformodelingthebehaviorofanalogcomponents.•Verilog-Aisaprocedurallanguage,withconstructssimilartoCandotherlanguages•ManyEDAsoftwareprovidersupportVerilog-A,suchasCadence,Angilent,Silvaco,Mentorandsoon.AllRightReserved•Verilog-AisasubsetofVerilog-AMS(AnalogMixedSignal)OVI--OpenVerilogInternationalAllRightReserved•Verilog-AisacircuitdesignorientedHIGHlevellanguage.•EnablescompactmodelingengineertoeasilydevelopproprietarySPICEmodelsforspecificsemiconductortechnologybehavior.•Ifcompile-complete,thesimulationspeedisclosetobuilt-inC-basedmodels.•Compiledcodeisinbinaryformatandtransportingthiscodewillprotecttheuser'sIP.AllRightReservedtypedefstructSPICEdev{IFdeviceDEVpublic;int(*DEVparam)();/*routinetoinputaparametertoadeviceinstance*/int(*DEVmodParam)();/*routinetoinputaparamatertoamodel*/int(*DEVload)();/*routinetoloadthedeviceintothematrix*/int(*DEVsetup)();/*setuproutinetopreprocessdevicesonce*/int(*DEVunsetup)();/*cleanupbeforerunningagain*/int(*DEVpzSetup)();/*setuproutineforpzanalysis*/int(*DEVtemperature)();/*temperaturedependentsetupprocessing*/int(*DEVtrunc)();/*subroutinetoperformtruncationerrorcalc.*/int(*DEVfindBranch)();/*subroutinetosearchfordevicebrancheq.s*/int(*DEVacLoad)();/*acanalysisloadingfunction*/int(*DEVaccept)();/*subroutinetocallonacceptanceofatimepoint*/void(*DEVdestroy)();/*subroutinetodestroyallmodelsandinstances*/int(*DEVmodDelete)();/*subroutinetodeleteamodelandallinstances*/int(*DEVdelete)();/*subroutinetodeleteaninstance*/int(*DEVsetic)();/*routinetopickupdeviceinitcondsfromrhs*/int(*DEVask)();/*routinetoaskaboutdevicedetails*/int(*DEVmodAsk)();/*routinetoaskaboutmodeldetails*/int(*DEVpzLoad)();/*routinetoloadforpole-zeroanalysis*/int(*DEVconvTest)();/*convergencetestfunction*/int(*DEVsenSetup)();/*routinetosetupthedevicesensitivityinfo*/int(*DEVsenLoad)();/*routinetoloadthedevicesensitivityinfo*/int(*DEVsenUpdate)();/*routinetoupdatethedevicesensitivityinfo*/int(*DEVsenAcLoad)();/*routinetoloadthedeviceacsensitivityinfo*/void(*DEVsenPrint)();/*subroutinetoprintoutsensitivityinfo*/int(*DEVsenTrunc)();/*subroutinetoprintoutsensitivityinfo*/int(*DEVdisto)();/*distortionroutine*/int(*DEVnoise)();/*noiseroutine*/int*DEVinstSize;/*sizeofaninstance*/int*DEVmodSize;/*sizeofamodel*/}SPICEdev;//DiodeModel`includeconstants.vams`includedisciplines.vamsmodulediode(pp,nn);inoutpp,nn;electricalpp,nn;parameterrealIs=1e-16;parameterrealvth=0.026;realVpn;analogbeginVpn=V(pp,nn);I(pp,nn)+Is*(exp(Vpn/vth)-1);endendmoduleNeedtoCompileWHOLEsoftwareNeedtoCompileONLYthisfileAllRightReserved•Verilog-Aoverview•Asimpleexample•Verilog-Asolution•Howtodescribethesystemstructure?•Howtodescribethecomponentbehavior?•UseVerilog-AinCadenceAllRightReserved//DiodeModel`includeconstants.vams`includedisciplines.vamsmodulediode(pp,nn);inoutpp,nn;electricalpp,nn;parameterrealIs=1e-16;parameterrealvth=0.026;realVpn;analogbeginVpn=V(pp,nn);I(pp,nn)+Is*(exp(Vpn/vth)-1);endendmodule//NetListsimulatorlang=spectreglobal0ahdl_include“diode.vaI0(01)isourcetype=dcI1(10)diodeIs=1e-15Dcdcdev=I0param=dcstart=1mstop=1ComponentModelDescriptionUsingVerilog-ACircuitNetListI1I0GNDAllRightReservedAllRightReserved//DiodeModel`includeconstants.vams`includedisciplines.vamsmodulediode(pp,nn);inoutpp,nn;electricalpp,nn;parameterrealIs=1e-16;parameterrealvth=0.026;realVpn;analogbeginVpn=V(pp,nn);I(pp,nn)+Is*(exp(Vpn/vth)-1);endendmoduleComment//thisisacomment/*thisisacomment*/Numbers:real,integerNote:CaseSensitiveAllRightReserved//DiodeModel`includeconstants.vams`includedisciplines.vamsmodulediode(pp,nn);inoutpp,nn;electricalpp,nn;parameterrealIs=1e-16;parameterrealvth=0.026;realVpn;analogbeginVpn=V(pp,nn);I(pp,nn)+Is*(exp(Vpn/vth)-1);endendmodule`include--compilerdirectivecommand`include“relativepath”`include“absolutepath”AllRightReserved//DiodeModel`includeconstants.vams`includedisciplines.vamsmodulediode(pp,nn);inoutpp,nn;electricalpp,nn;parameterrealIs=1e-16;parameterrealvth=0.026;realVpn;analogbeginVpn=V(pp,nn);I(pp,nn)+Is*(exp(Vpn/vth)-1);endendmodulemoduledeclarationmodulemodulename(portlist);portdirectiondeclare;porttypedeclare;parameterdeclare;….endmodulePortdirection:input,output,inoutPorttype:electrical,voltage,currentParameter:m11234w=10ul=1uAllRightReserved//DiodeModel`includeconstants.vams`includedisciplines.vamsmodulediode(pp,nn);inoutpp,nn;electricalpp,nn;parameterrealIs=1e-16;parameterrealvth=0.026;realVpn;analogbeginVpn=V(pp,nn);I(pp,nn)+Is*(exp(Vpn/vth)-1);endendmoduleDefiningModuleAnalogBehaviorVariabledefinitionAnalogbehaviordescriptionV(p1,pt2)accessthevoltagebetweenp1andp2I(p1,p2)accessthecurrentbetweenp1andp2“+“BranchContributionStatementAllRightReserved//NetListsimulatorlang=spectreglobal0ahdl_include“diode.va“I0(01)isourcetyp