a-Using-HSPICE-with-Verilog-A

HSPICE®SimulationandAnalysisUserGuide429X-2005.091212UsingHSPICEwithVerilog-ADescribeshowtouseVerilog-AinHSPICEsimulations.Verilog-Aisusedtocreateanduseanalogbehavioraldescriptionsthatencapsulatehigh-levelbehavioralandstructuraldescriptionsofsystemsandcomponents.Thelanguageallowsthebehaviorofeachmodel,ormodule,tobedescribedmathematicallyintermsofitsportsandparametersappliedtoaninstanceofthemodule.Amodulecanbedefinedatalevelofabstractionappropriateforthemodelandanalysis,includingarchitecturaldesign,andverification.Verilog-Asupportsbothatop-downdesignaswellasabottom-upverificationmethodology.Verilog-AwasderivedfromtheIEEE1364VerilogHardwareDescriptionLanguage(HDL)specificationandisintendedfordescribingbehaviorinanalogsystems.TheVerilog-AlanguagethatHSPICEsupportsiscomplianttoVerilog-AMSLRM2.1fromAccellerawithsomeLRM2.2featuresadded,suchas$table_model,$param_given,outputparameters,andtheabovefunction.TheVerilog-AimplementationinHSPICEsupportsamixeddesignofVerilog-Adescriptionsandtransistor-levelSPICEnetlistswithasimpleusemodel.MostanalysisfeaturesavailableinHSPICEaresupportedforVerilog-Abaseddevices,includingAC,DC,transientanalysis,statisticalanalysis,andoptimization.430HSPICE®SimulationandAnalysisUserGuideX-2005.0912:UsingHSPICEwithVerilog-AGettingStartedGettingStartedThissectionexplainshowtogetstartedusingacompactdevicemodelwritteninVerilog-AinHSPICE.Verilog-Adevicesusethefollowingconventions:■modulesareloadedintothesimulatorwitheitherthe.hdlnetlistcommandorthe–hdlHSPICEcommand-lineoption.■modulesareinstantiatedinthesamemannerasHSPICEsub-circuits.Thefirstcharacterforthenameofinstanceshouldbe“X”.■instanceandmodelparameterscanbemodifiedinthesamewayasotherHSPICEinstances.■modulenamesshouldnotconflictwithanyHSPICEbuilt-indevicekeyword(forexample,C,D,NMOS,PMOS,andsoon).Ifthishappens,HSPICEissuesawarningmessageandignorestheVerilog-Amoduledefinition.■nodevoltagesandbranchcurrentscanbeoutputusingconventionaloutputcommands.Note:BeforeyourunacircuitwithaVerilog-Amodule,checktobesurethatyourenvironmenthasbeensetuptosourcethecshrc.metafile.Fordetails,seetheHSPICEchaptertotheInstallationGuide.ThefollowingexampleillustrateshowacompactdevicemodelwritteninVerilog-AcanbeanalyzedwithHSPICE.Example:JFETCompactDeviceModelHSPICEcontainsalargenumberofcompactdevicemodelscodednativelyinthesimulator.Verilog-Aprovidesaconvenientmethodtointroducenewcompactmodels.TheJFETdevicemodelusesasimpleexpressiontorelatethesource-draincurrenttothegatevoltage.ThesimplifiedVerilog-Adescriptionofthismodelisshowninbelow.`includeconstants.vams`includedisciplines.vamsmodulejfet(d,g,s);parameterrealVto=-2.0from(-inf:inf);//ThresholdvoltageparameterrealBeta=1.0e-4from[0:inf);//TransconductanceparameterrealLambda=0.0from[0:inf);//Channelmodulationelectricald,g,s;HSPICE®SimulationandAnalysisUserGuide431X-2005.0912:UsingHSPICEwithVerilog-AGettingStartedrealId,Vgs,Vds;analogbeginVgs=V(g,s);Vds=V(d,s);if(Vds=Vgs-Vto)Id=Beta*(1+Lambda*Vds)*Vds*(2*(Vgs-Vto)-Vds);elseif(Vgs-VtoVds)Id=Beta*(1+Lambda*Vds)*(Vgs-Vto)*(Vgs-Vto);I(d,s)+Id;endendmoduleInthisexamplethemodulenameisjfetandthemodulehasthreeports,namedd,g,ands.Threeparameters,Vto,Beta,andLambda,canbepassedinfromthenetlist.Theelectricalbehaviorisdefinedbetweentheanalogbeginandendstatements.ThenodevoltagesacrossthegatetosourceanddraintosourceisaccessedandassignedtothevariablesVgsandVgd.Thesevaluesareusedtodeterminethedrain-sourcecurrent,Id.Thecalculatedcurrentiscontributedtothebranchfromdtosinthefinalstatementusingthecontributionoperator,+.ThisVerilog-AmoduleisloadedintoHSPICEwithan.HDLcommandinthenetlist.ThedeviceistheninstantiatedusingtheXprefixforthedevicename.Theconnectivity,modulename,andparameterassignmentsfollowtheformatofasub-circuitdevice.Thefollowinginstantiationlineinthenetlistisforthisdevice:x1draingatesourcejfetBeta=1.1e-4lambda=0.01Thenodesdrain,gate,andsourcearemappedtotheportsd,g,sinthesameorderasdefinedinthemoduledefinition.Anyparametersintheinstantiationlinearepassedtothemodule;otherwise,thedefaultvaluedefinedontheparameterdeclarationlineisused.Theparameterdeclarationallowsrangesandexclusionstobeeasilydefined.Theparameterpassedinfromthenetlististestedduringthesimulationandarun-timeerroroccursiftheparameterisoutoftheallowedrange.ThedeviceisusedintheHSPICEnetlistinexactlythesamemannerthatabuilt-indeviceisused.ThenetlistexampleshowninbelowperformsasimpleDC-IVanalysis.Verilog-AversionoftheSPICEJFET.hdljfet.va.optionspost=1VCCDrain03.0432HSPICE®SimulationandAnalysisUserGuideX-2005.0912:UsingHSPICEwithVerilog-AGettingStartedVGGate00.5VSSource00.0X1DrainGateSourcejfetVto=-2.0Beta=1.1e-4Lambda=0.01.dcVCC0.04.00.01VG-2.00.00.5.printI(VCC).endWhenthesimulationisperformed,theprogramcompilestheVerilog-Asourcefileintoacompiledobjectfile.ThisobjectfileisautomaticallycachedandsubsequentsimulationsdonotrequirethecompilestepunlesstheVerilog-Asourcefileismodified.Aftersimulation,HSPICEoutputsthedatainthesamefashionasotherdevices.Inthisexamplethedrain-sourcecurrentisplottedasafunctionofVdsandparameterizedb