SPI接口时序仿真

SPI接口时序仿真SPI接口数据交互讲授人:尤恺元SPI接口•SPI接口应用:•串行flash的读写擦除命令通过SPI接口进行通信。•CPU芯片与FPGA通过SPI接口进行通信。•其他功能集成电路芯片参数寄存器配置。某DAC芯片的SPI配置时序•SPI(SerialPeripheralInterface)•SCLK主机给从机的系统时钟•SDI主机输出给从机的数据•SDO从机输出给主机的数据某DAC芯片的SPI配置时序•CSchipselect片选信号，此信号可以使一个主机控制多个从机，此信号有效表示此从机被选中通信。SPI的时序某DAC芯片的SPI配置时序•R/W高表示读操作,低表示写操作•N1:N0传输Byte模式选择•A4:A0指示寄存器地址•D7:D0承载配置数据dac_ini_ctrl.v代码moduledac_ini_ctrl(inputwiresclk,inputwirerst_n,//work_eninputwirework_en,outputregconf_end,//spiinterfaceoutputwirespi_clk,outputregspi_sdi,outputregspi_cs,inputwirespi_sdo);parameterIDLE=5'b0000_1;parameterWAIT=5'b0001_0;parameterREAD_MEM=5'b0010_0;parameterWRITE=5'b0100_0;parameterSTOP=5'b1000_0;dac_ini_ctrl.v代码reg[4:0]state=0;reg[7:0]div_cnt=0;//spiclkregclk_p=0;wireclk_n;//cntreg[3:0]wait_cnt=0;reg[5:0]read_cnt=0;reg[3:0]shift_cnt=0;//endflagwirewait_end;regread_end=0;wireshift_end;reg[15:0]shift_data=0;wire[15:0]dout;regpose_flag;dac_ini_ctrl.v代码always@(posedgesclkornegedgerst_n)if(rst_n=='d0)div_cnt='d0;elseif(div_cnt==DIV_NUM)div_cnt='d0;elsediv_cnt=div_cnt+'d1;always@(posedgesclk)if(wait_end)wait_cnt='d0;elseif(state==WAIT&&pose_flag==1'b1)wait_cnt=wait_cnt+'d1;elseif(pose_flag==1'b1)wait_cnt='d0;always@(posedgesclk)if(state==READ_MEM)read_cnt=read_cnt+'d1;dac_ini_ctrl.v代码always@(posedgesclk)if(shift_end)shift_cnt='d0;elseif(state==WRITE&&pose_flag==1'b1)shift_cnt=shift_cnt+'d1;//latchdataalways@(posedgesclk)if(state==READ_MEM)shift_data=dout;elseif(state==WRITE&&pose_flag==1'b1)shift_data={shift_data[14:0],1'b0};//spiclkalways@(posedgesclk)if(div_cnt==DIV_NUM)clk_p=~clk_p;assignclk_n=~clk_p;dac_ini_ctrl.v代码//spiclkflagalways@(posedgesclkornegedgerst_n)if(rst_n==1'b0)pose_flag=1'b0;elseif(div_cnt==DIV_NUM-1&&clk_p==1'b0)pose_flag=1'b1;elsepose_flag=1'b0;//endflagassignwait_end=wait_cnt[3];always@(posedgesclk)if(read_cnt==READ_NUM&&pose_flag==1'b1)read_end='d1;assignshift_end=&shift_cnt&pose_flag;always@(posedgesclkornegedgerst_n)if(rst_n=='d0)state=IDLE;elsecase(state)IDLE:if(work_en)state=WAIT;WAIT:if(wait_end)state=READ_MEM;READ_MEM:state=WRITE;WRITE:if(shift_end&&read_end)state=STOP;elseif(shift_end)state=WAIT;STOP:state=STOP;default:state=IDLE;endcasedac_ini_16x32YourInstanceName(.a(read_cnt[4:0]),//Bus[4:0].d(1'b0),//Bus[15:0].clk(sclk),.we(1'b0),.spo(dout));//Bus[15:0]assignspi_clk=(spi_cs==1'd0)?clk_n:1'd0;always@(posedgesclk)if(state==WRITE&&pose_flag==1'b1)spi_cs='d0;elseif(pose_flag==1'b1)spi_cs='d1;always@(posedgesclk)if(state==WRITE&&pose_flag==1'b1)spi_sdi=shift_data[15];elseif(pose_flag==1'b1)spi_sdi='d0;always@(posedgesclk)if(state==STOP&&pose_flag==1'b1)conf_end=1'd1;elseif(pose_flag==1'b1)conf_end=1'd0;endmoduledac_ini_16x32IPcore•此IPcore需要ise生成dac_ini_16x32IPcore测试激励模块tb_dac_ini_ctrl.v`timescale1ns/1nsmoduletb_dac_ini_ctrl();regsclk,rst_n,work_en;wireconf_end,spi_clk,spi_sdi,spi_cs;initialbeginsclk=0;rst_n=0;work_en=0;#100rst_n=1;#100work_en=1;endalways#5sclk=~sclk;测试激励模块tb_dac_ini_ctrl.vdac_ini_ctrldac_ini_ctrl(.sclk(sclk),.rst_n(rst_n),.work_en(work_en),.conf_end(conf_end),.spi_clk(spi_clk),.spi_sdi(spi_sdi),.spi_cs(spi_cs),.spi_sdo(1'b0));endmodule仿真脚本run.do.mainclearquit-simvlibworkvmapworkworkvlogxilinx_lib/*.vvlog../ise_pro/ipcore_dir/*.vvlog../design/*.vvlogtb_dac_ini_ctrl.vvsim-voptargs=+accwork.tb_dac_ini_ctrlwork.glblviewstructureviewwaveviewsignals仿真脚本run.do#虚拟信号结构virtualtype{{1IDLE}{2WAIT}{4READ_MEM}{8WRITE}{10STOP}}dac_ctrl_state;addwave-noupdate-divider{topmoduledac_ini_ctrl}addwave-radixhexadecimaltb_dac_ini_ctrl/dac_ini_ctrl/*addwave-noupdate-divider{state}virtualfunction{(dac_ctrl_state)/tb_dac_ini_ctrl/dac_ini_ctrl/state}new_state_signaladdwave-radixhexadecimal-coloryellow/tb_dac_ini_ctrl/dac_ini_ctrl/new_state_signalrun1ms