全加器及半加器verilog

modulequanjiaqi(ain,bin,c,out);input[3:0]ain,bin;output[3:0]out;outputc;wirec1,c2,c3;fulladderu0(.a(ain[0]),.b(bin[0]),.cin(1'b0),.cout(c1),.out(out[0]));fulladderu1(.a(ain[1]),.b(bin[1]),.cin(c1),.cout(c2),.out(out[1]));fulladderu2(.a(ain[2]),.b(bin[2]),.cin(c2),.cout(c3),.out(out[2]));fulladderu3(.a(ain[2]),.b(bin[2]),.cin(c3),.cout(c),.out(out[3]));endmodulemodulefulladder(a,b,cin,out,cout);inputa,b,cin;outputcout,out;assignout=a^b^cin;assigncout=(a&b)|(a&cin)|(b&cin);endmodule`timescale1ns/1nsmoduletop;reg[3:0]ain,bin;wire[3:0]out;wirec;quanjiaqim(ain,bin,out,c);initialbeginain=4'b0000;bin=4'b0000;#100ain=4'b0111;bin=4'b0101;#100$stop;endendmodule°ë¼ÓÆ÷modulemux(a,b,sl,out);inputa,b,sl;outputout;assignout=(sl==0)?a:b;endmodulemoduleerjiaqi(a,b,c,sum);inputa,b;outputc,sum;muxu0(.a(a),.b(b),.sl(a),.out(c));muxu1(.a(~c),.b(a),.sl(~b),.out(sum));endmodule`timescale1ns/1nsmoduletop;rega,b;wirec,sum;erjiaqim(a,b,c,sum);initialbegina=0;b=0;#100a=1;b=0;#100a=1;b=1;#100a=0;b=1;#100$stop;endendmodule