规格书：H27U1G8F2B-(Rev0.1)-nand-flash

Thisdocumentisageneralproductdescriptionandissubjecttochangewithoutnotice.Hynixdoesnotassumeanyresponsibilityforuseofcircuitsdescribed.Nopatentlicensesareimplied.Rev0.1/Jul.200811PreliminaryH27U1G8F2BSeries1Gbit(128Mx8bit)NANDFlash1GbNANDFlashH27U1G8F2BRev0.1/Jul.200821PreliminaryH27U1G8F2BSeries1Gbit(128Mx8bit)NANDFlashDocumentTitle1Gbit(128Mx8bit)NANDFlashMemoryRevisionHistoryRevisionNo.HistoryDraftDateRemark0.0InitialDraft.May.13.2008Preliminary0.11)CorrectTable5.ModeSelection.Jul.4.2008PreliminaryCLEALECEWEREWPMODELLLHHXDuringRead(Busy)↓↓↓XXXHHXDuringRead(Busy)Rev0.1/Jul.200831PreliminaryH27U1G8F2BSeries1Gbit(128Mx8bit)NANDFlashFEATURESSUMMARYHIGHDENSITYNANDFLASHMEMORIES-CosteffectivesolutionsformassstorageapplicationsNANDINTERFACE-x8buswidth.-Address/DataMultiplexing-PinoutcompatiblityforalldensitiesSUPPLYVOLTAGE-3.3Vdevice:Vcc=2.7V~3.6VMEMORYCELLARRAY-(2K+64)bytesx64pagesx1024blocksPAGESIZE-(2K+64spare)BytesBLOCKSIZE-(128K+4Kspare)BytesPAGEREAD/PROGRAM-Randomaccess:25us(max.)-Sequentialaccess:25ns(min.)-Pageprogramtime:200us(typ.)FASTBLOCKERASE-Blockerasetime:2ms(Typ)ELECTRONICSIGNATURE-1stcycle:ManufacturerCode-2ndcycle:DeviceCode-3rdcycle:Internalchipnumber,CellType,NumberofSimultaneouslyProgrammedPages.-4thcycle:Pagesize,Blocksize,Organization,SparesizeCOPYBACKPROGRAM-FastDataCopywithoutexternalbufferingCACHEREAD-InternalbuffertoimprovethereadthroughputCHIPENABLEDON'TCARE-SimpleinterfacewithmicrocontrollerSTATUSREGISTER-NormalStatusRegister(Read/Program/Erase)HARDWAREDATAPROTECTION-Program/EraselockedduringPowertransitions.DATARETENTION-100,000Program/Erasecycles(with1bit/528byteECC)-10yearsDataRetentionPACKAGE-H27U1G8F2BTR-BX:48-PinTSOP1(12x20x1.2mm)-H27U1G8F2BTR-BX(Lead&HalogenFree)Rev0.1/Jul.200841PreliminaryH27U1G8F2BSeries1Gbit(128Mx8bit)NANDFlash1.SUMMARYDESCRIPTIONHynixNANDH27U1G8F2BSerieshave128Mx8bitwithspare4Mx8bitcapacity.Thedeviceisofferedin3.3VVccPowerSupply,andwithx8I/Ointerface.ItsNANDcellprovidesthemostcost-effectivesolutionforthesolidstatemassstoragemarket.Thememoryisdividedintoblocksthatcanbeerasedindependentlysoitispossibletopreservevaliddatawhileolddataiserased.Thedevicecontains1024blocks,composedby64pages.Aprogramoperationallowstowritethe2112bytepageintypical200usandaneraseoperationcanbeperformedintypical2.0msona128Kbyteblock.Datainthepagecanbereadoutat25nscycletimeperbyte.TheI/Opinsserveastheportsforaddressanddatainput/outputaswellascommandinput.Thisinterfaceallowsareducedpincountandeasymigrationtowardsdifferentdensities,withoutanyrearrangementoffootprint.Commands,DataandAddressesaresynchronouslyintroducedusingCE,WE,RE,ALEandCLEinputpin.Theon-chipProgram/EraseControllerautomatesallprogramanderasefunctionsincludingpulserepetition,whererequired,andinter-nalverificationandmarginingofdata.ThemodifyoperationscanbelockedusingtheWPinput.ThechipsupportsCEdon'tcarefunction.ThisfunctionallowsthedirectdownloadofthecodefromtheNANDFlashmemorydevicebyamicrocontroller,sincetheCEtransitionsdonotstopthereadoperation.TheoutputpinR/B(opendrainbuffer)signalsthestatusofthedeviceduringeachoperation.InasystemwithmultiplememoriestheR/Bpinscanbeconnectedalltogethertoprovideaglobalstatussignal.Eventhewrite-intensivesystemscantakeadvantageoftheH27U1G8F2BSeriesextendedreliabilityof100Kprogram/erasecyclesbyprovidingECC(ErrorCorrectingCode)withrealtimemapping-outalgorithm.Thecopybackfunctionallowstheoptimizationofdefectiveblocksmanagement:whenapageprogramoperationfailsthedatacanbedirectlyprogrammedinanotherpageinsidethesamearraysectionwithoutthetimeconsumingserialdatainsertionphase.Datareadoutaftercopybackreadisallowed.ThisdeviceincludesalsoextrafeatureslikeOTP/UniqueIDarea,ReadID2extension.TheH27U1G8F2Bisavailablein48-TSOP112x20mm.1.1ProductListPARTNUMBERORGANIZATIONVccRANGEPACKAGEH27U1G8F2Bx82.7V~3.6V48-TSOP1Rev0.1/Jul.200851PreliminaryH27U1G8F2BSeries1Gbit(128Mx8bit)NANDFlashVCCVSSWPCLEALEREWECEIO0~IO7R/BFigure2:48-TSOP1Contact,x8DeviceIO7-IO0DataInput/OutputsCLECommandlatchenableALEAddresslatchenableCEChipEnableREReadEnableWEWriteEnableWPWriteProtectR/BReady/BusyVccPowerSupplyVssGroundNCNoConnectionFigure1:LogicDiagramTable1:SignalNames1&1&1&1&1&1&5%5(&(1&1&9FF9VV1&1&&/($/(:(:31&1&1&1&1&1&1&1&1&,2,2,2,21&1&1&9FF9VV1&1&1&,2,2,2,21&1&1&1&1$1')ODVK7623[Rev0.1/Jul.200861PreliminaryH27U1G8F2BSeries1Gbit(128Mx8bit)NANDFlash1.2PINDESCRIPTIONTable2:PinDescriptionNOTE:1.A0.1uFcapacitorshouldbeconnectedbetweentheVccSupplyVoltagepinandtheVssGroundpintodecouplethecurrentsurgesfromthepowersupply.ThePCBtrackwidthsmustbesufficienttocarrythecurrentsrequiredduringprogramanderaseoperations.PinNameDescriptionIO0~IO7DATAINPUTS/OUTPUTSTheIOpinsallowtoinputcommand,addressanddataandtooutputdataduringread/programoperations.TheinputsarelatchedontherisingedgeofWriteEnable(WE).TheI/ObufferfloattoHigh-Zwhenthedeviceisdeselectedortheoutputsaredisabled.CLECOMMANDLATCHENABLEThisinputactivatesthelatchingoftheIOinputsinsidetheCommandRegisterontheRisingedgeofWriteEnable(WE).ALEADDRESSLATCHENABLEThis