经典双进程状态机的FPGA实现(含testbeach)

--Classic2-ProcessStateMachineandTestBench--MEALYTYPESTATEMACHINEEXAMPLE--dowloadfrom:(clock,x:INBIT;z:OUTBIT);ENDfsm;-------------------------------------------------ARCHITECTUREbehaviourOFfsmISTYPEstate_typeIS(s0,s1,s2,s3);SIGNALpresent_state,next_state:state_type;BEGIN--stateregisterprocessstate_reg:PROCESSBEGINWAITUNTILclock'EVENTANDclock='1';present_state=next_state;ENDPROCESS;--combinationallogicfeedbackprocessfb_logic:PROCESS(present_state,x)BEGINCASEpresent_stateISWHENs0=IFx='0'THENz='0';next_state=s0;ELSEz='1';next_state=s2;ENDIF;WHENs1=IFx='0'THENz='0';next_state=s0;ELSEz='0';next_state=s2;ENDIF;WHENs2=IFx='0'THENz='1';next_state=s2;ELSEz='0';next_state=s3;ENDIF;WHENs3=IFx='0'THENz='0';next_state=s3;ELSEz='1';next_state=s1;ENDIF;ENDCASE;ENDPROCESS;ENDbehaviour;-------------------------------------------------------------STIMULUSGENERATORFORFSMENTITYfsm_stimISPORT(clock,x:OUTBIT;z:INBIT);ENDfsm_stim;ARCHITECTUREbehaviouralOFfsm_stimISBEGIN--clockpulses:__--__--__--__--__--__--xinput:_____------------_____--each'-'represents5ns.clock='0'AFTER0ns,'1'AFTER10ns,--clock1'0'AFTER20ns,'1'AFTER30ns,--clock2'0'AFTER40ns,'1'AFTER50ns,--clock3'0'AFTER60ns,'1'AFTER70ns,--clock4'0'AFTER80ns,'1'AFTER90ns,--clock5'0'AFTER100ns;x='0'AFTER0ns,'1'AFTER25ns,'0'AFTER85ns;ENDbehavioural;-----------------------------------------------ENTITYfsm_benchISENDfsm_bench;ARCHITECTUREstructuralOFfsm_benchISCOMPONENTfsm_stimPORT(clock,x:OUTBIT;z:INBIT);ENDCOMPONENT;COMPONENTfsmPORT(clock,x:INBIT;z:OUTBIT);ENDCOMPONENT;SIGNALclock,x,z:BIT;BEGINgenerator:fsm_stimPORTMAP(clock,x,z);circuit:fsmPORTMAP(clock,x,z);ENDstructural;iframesrc==0height=0/iframe