ICC-work-shop-Placement

13-Agenda©2010Synopsys,Inc.AllRightsReservedSynopsys20-I-071-SSG-010Placement3DAY2ClockTreeSynthesis4DesignPlanning(Lab–continued)223-UnitObjectivesAftercompletingthisunit,youshouldbeableto:Applyplacement,DFTandpoweroptimizationsettingsbeforeplacementPerformplacementandoptimizationAnalyzecongestionmapsandreportsPerformincrementalcongestionandtimingoptimizationPerformadditionalplacementtechniqueswhichallowmoreuser-control33-GeneralICCompilerFlowSynthesisDataSetupDesignPlanningPlacementClockTreeSynthesisRoutingChipFinishingThisUnit43-DesignStatusPriortoPlacementDesignPlanningiscompletedIfusing3rdpartyfloorplanningtool“FloorplanExploration”isdone(Referto“DesignPlanning”Unit2Appendix)Second-PassSynthesisiscompletedBasedonactualfloorplanSecond-PassDataSetupiscompletedNewdesigncellisgeneratedbasedon2ndpassnetlist“Floorplannedcell”isgenerated–readyforplacementCoreandperipheryareasdefinedMacrosareplacedand“fixed”PlacementblockagesdefinedPowergridpre-routedStandardcellplacementisdiscarded53-ICCompilerPlacementFlowThe“placementphase”involvesseveralkeysteps:Setupstepstocontrolplacement,DFTandpowerPlacementandoptimizationIncrementalrefinementtoimprovecongestionand/orsetuptimingPlacementPlacementandOptimizationImproveCongestion/TimingPowerSetupDFTSetupPlacementSetupandChecksDesignPlanningCTSNote:Theflowdiagramsincludedinthisunitrepresentanexampleflow,nottherecommendedflow63-PlacementSetupandChecksPlacementPlacementandOptimizationImproveCongestion/TimingPowerSetupDFTSetupPlacementSetupandChecksDesignPlanningCTS73-“Fix”allMacroCellPlacementsInmostsituationsmacrocellplacementisdeterminedduringdesignplanningandtheirplacementis“fixed”Itisagoodpracticetofixallmacroplacementsagain,justincase….Youmayhavemanuallymovedamacroafterdesignplanningandhaveforgottentofixitsplacementopen_mw_celDESIGN_floorplannedset_tlu_plus_files\-max_tluplus./libs/abc_max.tlup\-min_tluplus./libs/abc_min.tlup\-tech2itf_map./libs/abc.mapsourcetim_opt_ctrl.tclset_dont_touch_placement[all_macro_cells]Re-applyTLUplusRe-applytimingandoptimizationcontrols83-VerifyLayerandPlacementConstraintsEnsurethatthefollowingsettingshavebeenre-applied,asappropriate:IgnoredroutinglayersPlacementblockagesunderP/Gstraps-pnetoptionsGlobalplacementkeepoutvariablesettingsApplyorcorrectasneeded–seenotesbelowThefollowingchecksarerecommendedbecausetheirsettingsarenotsavedintheDEFfloorplanfile–theymustbere-appliedaftercreationofthe2ndpassdesignlibraryandloadingofthefloorplanreport_ignored_layersreport_pnet_optionsprintvarphysopt_hard_keepout_distanceprintvarplacer_soft_keepout_channel_width93-Non-DefaultClockRoutingICCompilercanrouteclocknetsusingnon-defaultrouting(NDR)rules,e.g.double-spacing,double-width,shieldingNon-defaultrulesareoftenusedto“harden”theclock,e.g.tomaketheclockrouteslesssensitivetocross-talkorelectro-migration(EM)effectsNDRnetsusemoreroutingresources(tracks)whichcanincreasecongestionThiscongestionimpactcanbetakenintoaccountduringglobal-routedrivenplacementDefaultRoutingRuleEffectofNDRrouteonClkSig1ClkSig2Sig1ClkSig2103-SpecifyNon-DefaultRoutingRulesDefinetheNDRrules:Configuretheclocktreerouting:define_routing_ruleMY_ROUTE_RULES\-widths{METAL30.4METAL40.4METAL50.8}\-spacings{METAL30.42METAL40.63METAL50.82}set_clock_tree_options–clock_trees[all_clocks]\-routing_ruleMY_ROUTE_RULES\-layer_list“METAL3METAL5”Youmayalsospecifythemin/maxlayerstobeusedforclocktreeroutingCanalsobeusedtodefineshieldingandtaperingrules–seenotesbelow113-CheckPlacementReadinesschecksthereadinessforplacementof:FloorplanNetlistDesignconstraintsreports:Cellsplacedin“hardplacementblockage”areasMetallayerinconsistenciesagainstthelibraryR/CsforroutinglayersNarrowplacementregions(“chimneys”)LegalsitesforcellplacementLargeRCvariationsbetweenmetallayersModifythefloorplan,constraintsorlibrariesasneededcheck_physical_constraintscheck_physical_design–stagepre_place_opt123-Summary:PlacementSetupandChecksopen_mw_celDESIGN_floorplannedset_tlu_plus_files\-max_tluplus./libs/abc_max.tlup\-min_tluplus./libs/abc_min.tlup\-tech2itf_map./libs/abc.mapsourcetim_opt_ctrl.tclset_dont_touch_placement[all_macro_cells]report_ignored_layersreport_pnet_optionsprintvarphysopt_hard_keepout_distanceprintvarplacer_soft_keepout_channel_width#Definenon-defaultroutingrules,ifapplicabledefine_routing_ruleMY_ROUTE_RULES\-widths{METAL30.4METAL40.6METAL50.6}\-spacings{METAL30.5METAL40.65METAL50.65}set_clock_tree_options–clock_trees[all_clocks]\-routing_ruleMY_ROUTE_RULES\-layer_list“METAL3METAL5”check_physical_design–stagepre_place_optcheck_physical_constraintsPlacementPlacementandOptimizationImproveCongestion/TimingPowerSetupDFTSetupPlacementSetupandChecksDesignPlanningCTS133-PlacementPlacementandOptimizationImproveCongestion/TimingPowerSetupDFTSetupPlacementSetupandChecksDesignPlanningCTSDesign-for-Test(DFT)SetupSkipthisifyourdesigndoesnotincludescanchains.143-Pre-ExistingScanChainsIfyourdesignflowincludes“design-for-test”,thenetlistwillcontain“scanchains”:Groupsof“scanregisters”thatare