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华中科技大学硕士学位论文基于MIPS指令集的RISC微处理器数据通路的设计与实现姓名:刘宁申请学位级别:硕士专业:计算机应用技术指导教师:曹计昌20080603ISOCSOCMIPSMIPSMIPSRISCMIPS,16RISCMIPSFPGA3440MHZIIAbstractWiththedevelopmentofintegratedcircuittechnology,SOCdesignbecomesmoreandmorepopular.TheSOC-basedapproachtoembeddedsystemdesignreducesthecostofdevelopmentsignificantly,italsomakesmaintainanceeasier.Themicroprocessoristhecoreofembeddedsystems,itdeterminestheperformanceoftheentireembeddedsystem.TheMIPSinstructionformatisclearandcompact;itcansimplifythedesignofthemicroprocessorarchitecture,andachievesrelativelygoodperformance.TheultimatedesignisbasedontheMIPSinstructionset,andithasfivestagespipeline.BasedontheresearchofMIPSinstructionset,instructionsandinstructionaddressinghasbeenchosentoimplement.Thedetailedanalysisofexecution,thefunctionalunitdesignedincludes:thememoryunitofinstructionanddata,theregisterfilesprovidinghigh-speedoperation,thearithmeticlogicalunit,thesignextendunit.Weimplementthedatapathofsinglecycleriskprocessorafterallthemodulesaredesigned.Asweknow,thepipelineisthemostimportantmethodtoimprovetheperformanceoftheembeddedmicroprocessor.Aftercompletionofsinglecycleprocessordatapath,wecarefullyanalyzeanddesignthepipelineprocessordatapathandregisters,andeventuallyrealizedthefivestagespipelineprocessordatapath.Afterthedesigniscompleted,wesimulateallthemodules,anddownloaditintotheFPGAdevelopmentboard.Thefinaldatapathofthedesignsupports34instructionsintotal,andreachesitshighestfrequency40MHZ.KeyWords:SOC,RISCprocessor,pipeline,datapath_____111.1832FPGA(FieldProgrammableGateArray)FPGAMIPSMicroprocessorwithoutinterlockedpipedstages)MIPSFPGAMIPSFPGAFPGA,,FPGA,FPGAFPGAFPGA21.2MIPSRISCFPGAFPGA1.2.1CPUCISC[1](ComplexInstructionSetComputer)RISC[2](ReducedInstructionSetComputer)CISCCISCCISCx86IntelCISCIntelRISCCISCCISCCISC[3][4]RISCRISC[5]RISCRISC20%20%80%RISC[6,7]3RISCRISCDavidA.PaterrsonRISCRISCRISCIBMPowePC[8]HPPA-RISC[9]SUNSPARC[10]MIPSMIPSCISCRISC[11,12]12345678RISCloadstoreCISC9RISCMIPSRISCMIPSMIPSMIPSMIPSMIPSMIPS1.2.2SUNSPARCMIPSMIPSARM(AdvancedRISCMachinesLimitedARM)ARMPowerPC4RISC32RISC(FDU32)ARM7TDMI511%67%87%46%FPGA[13]ECOMIPSMIPS324GBBlockRAM64MHZ[14]32RISC25200kLEDLCDIC[15][16]CHandel-CMIPSMIPSMIPSMIPS[17]NPU1750A161646ATERAFPGA16[18][19]FPGA32CPU30MHZ1507%PowerPCR2VxWorksRTLcornercase[20]32RISCTS-1ALTERAFPGA536.7MHZ[21][22,23,24]HDL[25]FPGA1.2.3FPGA2060XilinxFPGA/CPLD[26]1985PLDCMOSFPGAHDLFPGA[27]IC[28]EDA[29,30,31]12RTLRTL6RTL3VHDL[32]Verilog451.1RTLRTL1.1FPGARTLFPGARTLRTL1.3MIPSRISC71FPGARISC212345bitFPGAMIPS32[33]RISCMIPS32RISC82MIPSMIPSMIPS2.1MIPSRIJ2.16165opimmediatersrt665555opfunctshamtrdrtrs626opaddressRIJ2.1MIPS2.12.1oprs1rt2rdshamtfunctRimmediateIaddressJPC9RILWSWPCPC2.2opfunctshamtrdrtrsoprsrtimmediateopinstr_index+PC:2.22.232-bitloadstoreRIMIPS1RI2I3IPCJ266104CPOR18I15J134562.22.2style[31..26][25..21][20..16][15..11][10..6][5..0]Roprsrtrdshamtfunctionnop00000000000000000000000000000000add000000rsrtrd00000100000addu000000rsrttd00000100001sub000000rsrtrd00000100010subu000000rsrttd00000100011and000000rsrtrd00000100100or000000rsrtrd00000100101xor000000rsrtrd00000100110nor000000rsrtrd00000100111slt000000rsrtrd00000101010sltu000000rsrtrd00000101011sll00000000000rtrdsa000000srl00000000000rtrdsa000010sra00000000000rtrdsa000011sllv000000rsrtrd00000000100srlv000000rsrtrd00000000110srav000000rsrtrd00000000111jr000000rs000000000000000001000rsstyle-Ioprsimmbltz000001rs00000immbgez000001rs00001immblez000110rs00000immbgtz000111rs00000immbeq000100rsrtimmbne000101rsrtimmaddi001000rsrtimmaddiu001001rsrtimmandi001100rsrtimmori001101rsrtimmxori001110rsrtimm112.2slti001010rsrtimmsltiu001011rsrtimmlw100011basertoffsetsw101011basertoffsetJopinstr_indexj000010addressaddress2.3[34,35,36]mmnmnm+n-1(nm)nmm[37,38](stage)mmm(2.1)m1nmnm≈−+×==t(2.1)2.2MIPS12IFins1ins2IDEXMEMWBtimeIFIDEXMEMWBIFIDEXMEMWBIFIDEXMEMWBIFIDEXMEMWBins3ins4ins52.2RISCStep1IFINSMem[PC]PCNewPCPC+4PCStep2IDARegs[INS10..6]ABRegs[INS16..11]BImmextend((INS15..0)32)Step3EXMemALUOutputA+extend((INS15..0)32)Mem[ALUOutput]DataMemRALUOutputAopBABI:ALUOutputAopextend((INS15..0)32)AJALUOutputPC+(extend(INS15..0)32)ifconditionistrue13NewPCALUOutputStep4MEMMem:ifloadMDBMem[ALUOutput]elsestoreMem[ALUOutput]MDBif(conditon)thenPCNewPCelsePCPC+4Step5WBRegRegs[INS20..16]ALUOutputImmRegs[INS15..11]ALUOutputMemRegs[INS15..11]MDB2.3IR=mem[PC];PC=PC+4A=Reg[IRrs];B=Reg[IRrt]r=AopIRopBr=AopIRopIRimr=A+IRimPC=IRjaddrifcom(A,b)PC=PC+IRimWB=rWB=rWB=Mem[r]Reg[IRrd]=WBReg[IRrd]=WBReg[IRrd]=WBfetchdecodeexecuteaccessmemorywritebacklw,swrirrjbranch2.3514123456782.4MIPS1533.1RISC16LWLW3.1PC+4InstructionMemoryDecodersrtRegistersALUimmDataMemoryrd1wdaddr3.1LW163.23.2.11n(n1)2n21(3.1)Cout=xy+(x|y)Cin3.1xy1x|y1|43.2~3.5C1=G0+P0C0=G0+P0Cin3.2C2=G1+P1C1=G1+P1G0+P1P0Cin3.3C3=G2+P2C2=G2+P2G1+P2P1G0+P2P1P0Cin3.4C4=G3+P3C3=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C-13.5Pn=XnYnGn=Xn|YnGiG*P*nFn^(3.6)~(3.8)17P*=X3X2X1X03.6G*=Y3+Y2X3+Y1X2X3+Y0X1X2X33.7Fn=Xn^Yn^Cn3.843.2C-13.2~3.8C3C2C1C0C-1G3G2G1G0P3P2P1P0P*X3X2X1X0Y2Y1Y3Y0G*3.241643.2163.9~3.
本文标题:基于MIPS指令集的RISC微处理器数据通路的设计与实现
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