实验1EDA工具的使用-

1实验1EDA工具的使用一、实验目的通过使用VerilogHDL语言创建一个简单的数字电路来了解XilinxVivado软件的使用方法，掌握其设计流程。一个典型的设计流程包括（如图1所示）：模型创建、添加用户约束文件、创建一个Vivado工程、输入所创建的电路模型、对用户约束文件添加约束、行为仿真、设计综合、设计实现、生成下载文件，最后是将下载文件下载到硬件平台上进行实际验证。图1设计流程图二、实验内容1.创建一个Vivad工程，对设计源文件进行分析；2.使用XSim仿真器对设计进行仿真；3.设计综合；4.设计实现；5.进行时序仿真；6.生成下载文件。三、实验步骤使用现成的设计文件针对XC7A100TCSG324C-1器件完成整个设计流程。电路如图2所示，部分输入通过逻辑处理后送到输出。具体操作步骤如下：2图2整个电路图3.1用IDE创建一个Vivado工程1.OpenVivadobyselectingStartAllProgramsXilinxDesignToolsVivado2014.2Vivado2014.22.ClickCreateNewProjecttostartthewizard.YouwillseeCreateANewVivadoProjectdialogbox.ClickNext.3.ClicktheBrowsebuttonoftheProjectlocationfieldoftheNewProjectform,browseto,forexampled:\Lab1_source,andclickSelect.4.EntertutorialintheProjectnamefield.MakesurethattheCreateProjectSubdirectoryboxischecked.ClickNext.5.SelectRTLProjectoptionintheProjectTypeform,andclickNext.6.SelectVerilogastheTargetlanguageandSimulatorlanguageintheAdd3Sourcesform.7.ClickontheAddFiles…button,browsetothed:\Lab1_sourcedirectory,selecttutorial.v,clickOpen,andthenclickNext.8.ClickNexttogettotheAddConstraintsform.9.ClickNextiftheentryisalreadyauto-populated,otherwiseclickontheAddFiles…button,browsetothed:\Lab1_sourcedirectoryandselecttutorial.xdc,andclickOpen.10.IntheDefaultPartform,usingthePartsoptionandvariousdrop-downfieldsoftheFiltersection,selecttheXC7A100TCSG324-1part.ClickNext.11.ClickFinishtocreatetheVivadoproject.12.Openthetutorial.vsourceandanalyzethecontent.13.Openthetutorial.xdcsourceandanalyzethecontent.14.PerformRTLanalysisonthesourcefile.ExpandtheOpenElaboratedDesignentryundertheRTLAnalysistasksoftheFlowNavigatorpaneandclickonSchematic.Themodel(design)willbeelaboratedandalogicviewofthedesignisdisplayed.NoticethatsomeoftheswitchinputsgothroughgatesbeforebeingoutputtoLEDsandtherestgostraightthroughtoLEDsasmodeledinthefile.43.2用XSimSimulator对设计进行仿真1.Addthetutorial_tb.vtestbenchfile.ClickAddSourcesundertheProjectManagertasksoftheFlowNavigatorpane.SelecttheAddorCreateSimulationSourcesoptionandclickNext.IntheAddSourcesFilesform,clicktheAddFiles…Button.Browsetothed:\Lab1_sourcefolderandselecttutorial_tb.vandclickOK.ClickFinish.2.SelecttheSourcestabandexpandtheSimulationSourcesgroup.Thetutorial_tb.vfileisaddedundertheSimulationSourcesgroup,andtutorial.visautomaticallyplacedinitshierarchyasatut1instance.53.Double-clickonthetutorial_tbintheSourcespanetoviewitscontents.Thetestbenchdefinesthesimulationstepsizeandtheresolutioninline1.Thetestbenchmoduledefinitionbeginsonline5.Line15instantiatestheDUT(device/moduleundertest).Lines17through26definethesamemodulefunctionalityfortheexpectedvaluecomputation.Lines28through39definethestimuligenerationandcomparestheexpectedoutputwithwhattheDUPprovides.Line41endsthetestbench.The$displaytaskwillprintthemessageinthesimulatorconsolewindowwhenthesimulationisrun.4.Simulatethedesignfor200nsusingtheXSimsimulator.SelectSimulationSettingsundertheProjectManagertasksoftheFlowNavigatorpane.AProjectSettingsformwillappearshowingtheSimulationpropertiesform.Selectthe6Simulationtab,andsettheSimulationRunTimevalueto200nsandclickOK.ClickonRunSimulationRunBehavioralSimulationundertheProjectManagertasksoftheFlowNavigatorpane.ThetestbenchandsourcefileswillbecompiledandtheXSimsimulatorwillberun(assumingnoerrors).Youwillseeasimulatoroutputsimilartotheoneshownbelow.5.ClickontheZoomFitbutton()locatedleftofthewaveformwindowtoseetheentirewaveform.6.Changedisplayformatifdesired.Selecti[31:0]inthewaveformwindow,right-click,selectRadix,andthenselectUnsignedDecimaltoviewthefor-loopindexinintegerform.Similarly,changetheradixofswitches[7:0]toHexadecimal.Leavetheleds[7:0]ande_led[7:0]radixtobinaryaswewanttoseeeachoutputbit.7.Addmoresignalstomonitorlower-levelsignalsandcontinuetorunthesimulationfor500ns.Expandthetutorial_tbinstance,ifnecessary,intheScopeswindowandselectthetut1instance.Theswt[7:0]andled[7:0]signalswillbedisplayedintheObjectswindow.Selectswt[7:0]andled[7:0]anddragthemintothewaveformwindowtomonitorthoselower-levelsignals.Onthesimulatortoolbuttonsribbonbar,type500inthetimewindow,clickonthedrop-downbuttonoftheunitsfieldandselectns,andclickonthe()button.78.Thesimulationwillrunforanadditional500ns.ClickontheZoomFitbuttonandobservetheoutput.9.ClosethesimulatorbyselectingFileCloseSimulation.ClickOKandthenclickNotocloseitwithoutsavingthewaveform.3.3设计综合1.ClickonRunSynthesisundertheSynthesistasksoftheFlowNavigatorpane.2.SelecttheOpenSynthesizedDesignoptionandclickOKaswewanttolookatthesynthesisoutputbeforeprogressingtotheimplementationstage.ClickYestoclosetheelaborateddesignifthedialogboxisdisplayed.3.SelecttheProjectSummarytab(SelectdefaultlayoutifthetabIsnotvisible)andunderstandthevariouswindows.84.ClickonSchematicundertheOpenSynthesizedDesigntasksofSynthesistasksoftheFlowNavigatorpanetoviewthesynthesizeddesigninaschematicview.3.4设计实现1.ClickonRunImplementationundertheImplementationtasksoftheFlowNavigatorpane.Theimplementationprocesswillberunonthesynthesisoutputfiles.WhentheprocessiscompletedanImplementationCompleteddialogboxwiththreeoptionswillbedisplayed.2.SelectO