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SIGMA-DELTAADC09/10DATACONVERTERNyquist-rateonetoonecorrespondence,nomemory;samplingratefs>2*fB;linearityandaccuracydeterminedbythematchingaccuracy→14to16bits;integratingorcountingonescanachieve18bits→2Nperiods;integralnonlinearityINL<0.5LSB.oversampledgeneratingeachoutpututilizingallprecedinginputvalues→memorycell;samplingratefsmuchhigherthantheNyquistrate→OSR=8~512;matchingaccuracyisrelaxedrelatively;canachieveover20bitsathighconversionspeeds→cost:fasteroperationandaddeddigitalcircuitry→gettingcheaper;signaltonoiseratioforasine-waveinput:SNR=6.02ENOB+1.76.OVERSAMPLINGMODULATORdeltamodulatorADC→nonlinear,memory→dynamic;qualitativeunderstanding→linearizedmodel;thenameof‘delta’:→thedifferenceoftwoneighboringsampleddata→largerinputsignal;loopfilterinfeedbackpath→limitedlinearityandaccuracy;demodulatorconsistingofaDACandafilter→thefilterwillamplifythenonlineardistortionoftheDAC;)()(11)()(uzvzezzvz)1()()1()()(vnenenununOVERSAMPLINGMODULATORsigmadeltamodulatorloopfilterintheforwardpathoftheloop;thenameof‘sigma-delta’or‘delta-sigma’thesignalisnotchanged(justdelayed)→thedemodulatordoesnotneedanintegrator→noamplificationofin-bandnoiseanddistortion;Δeissuppressedatfrequenciessmallcomparedtothesamplingratefs.→noiseshapingnonlinearityofADC→combinedwithe→shaping;nonlinearityofDAC→affectsoutputdirectly→majorlimitation.)1()()1()(vnenenunQUANTIZATIONERROR)1()()(qnenen)()1()(1zEzzQTjef2z)())sin(2()(S2fSfTfeqfirstordermodulator2/)(2srmsefefS3222)(3OSReqrmsrmssecondordermodulator)()1()()(211zEzzUzzV)())sin(2()(S4fSfTfeq5242)(5OSReqrmsrmsLthordermodulator12222))(12(LrmsLrmsOSRLeqDoublingtheOSRreducesthenoiseby9dB.→1.5bitsDoublingtheOSRreducesthenoiseby15dB.→2.5bitsDoublingtheOSRreducesthenoiseby(6L+3)dB.→(L+0.5)bitsSTABILITYCONSIDERATIONActually,forhigh-order,single-bitmodulators,stabilityconsiderationsreducetheachievableresolutiontoalowervalue,andthedifferencecanbesubstantial,amountingtomorethan60dBfora5th-ordermodulator.Whenu(n)approachestheno-overloadrange,Qemaypushy(n)intoit.linearmodelsolution:root-locus,BodeplotandNyquistplot.nonlinearsystem(thequantizergainissignal-dependent)→extensivesimulations:worst-caseinputsignal—aspecialsquarewave)()1)(()()()(zEzNTFzUzSTFzYMASHMODULATORSMASH(Multi-stAgenoiseSHaping)structurecaneasethestabilityproblemsmentionedbefore.)()()()()(1111zEzNTFzUzSTFzV)()()()()(22122zEzNTFzEzSTFzV02211STFHNTFHIf,E1(z)iscancelledintheoveralloutputV(z).Thenoise-shapingperformanceisthatofafourth-ordersingle-loopconverter,butitsstabilitybehavioristhatofasecond-orderone.imperfectionsintherealizationoftheTFs↓deteriorationofthenoiseperformanceMULTI-BITQUANTIZATIONsingle-bitquantizer(comparator)ill-definedgainfactor→changingloopgains→stabilityproblems→reductionoftheinputsignalswing→reductionintheachievableSNR.multi-bitquantizerwell-definedgain→stabilityisguaranteed/no-overloadrangeincreased;quantizationnoisedecreasingby6dBforeachbitaddedtothequantizer;problem:nonlinearity→mismatchshaping(similartonoiseshaping).TheinputoftheDACisexactlytheoutputofthemodulator,andthein-bandpartoftheDACoutputsignalisforcedtofollowtheinputsignalveryaccurately.Hence,iftheDACisnonlinear,itsinput,whichistheoveralloutput,mustbedistortedtogiveanaccurateoutput.Thatistosay,theDAC’snonlinearityaffectsthenoiseperformancedirectly,withoutbeingshaped.DIGITALFILTERout-of-bandnoisemustberemoved;outputsignalbedecimatedtoNyquistrate;requirementsontheLPFs:gain→flatandlargeoverthesignalband[0,fB],andsmallbetweenfBandfs/2;phase→flatgroupdelay;linear-phaseFIRfilter→sincfilters(mostoftenused).10)(1)(NiinvNnw11111)(zzNzHN)sinc()sinc()(21fNfeHfjOSRN)()1(1)()()()(11zEzNzEzNTFzHzQN)]()([1)(1NneneNnq22221Neq32223Neq212)111()(zzNzHN32222NeqAsincL+1LPFissufficientforanLth-orderloop.HISTORYfirstproposedin1962byInose(40dBSNR,5kHzbandwidth);12yearslater,higher-orderloopfiltersproposed;Adamsdescribedan18-bitΔΣADCin1986;MASHwasfirstappliedin1986.multi-bitquantizerwithdigitallinearitycorrectionproposedin1988;Variousmismatch-shapingalgorithmsweresuggestedsubsequently.参数及时序确定电路各参数——SDToolbox从工具箱基于Fs和OSR产生归一化的环路参数,再将输入信号幅度、积分器摆幅和反馈电压幅度等因素折算进去,并进行近似(可实现的电容比),得到参数为:a1=b1=1/4,a2=1/6,c1=1/4.理想性能(1)MATLAB行为级模型理想性能(2)Cadence中理想模块电路非理想因素(1)KT/C噪声主要噪声源设第一级输入电容(单边)大小为C1,则其所造成的信带内的KT/C噪声为:对于幅度为A的正弦输入信号,若要求达到某一SNR值(dB表示),留B(dB)的余量,则:非理想因素(2)运放非理想因素(主要是第一积分器的运放)运放增益:>OSR大的增益有利于电荷充分转移,从而减小谐波失真;增益带宽积:SC电路普遍要求GBW>10Fs;压摆率:SR要满足大信号建立的需求,否则会产生较大的谐波失真;热噪声:设计低噪声运放,减小热噪声的影响。谐波失真的来源多位量化时,量化间距的不匹配;一位量化时,比较器的增益非线性;(固有非线性)压摆率较小时,大信号建立不充分;电容非线性和增益非线性;开关电荷注入和运放输出饱和;非理想因素(3)MATLAB行为级模型(非理想)在理想环路的基础上,引入了Jitter、KTC、OpNoise、第一积分器的GBW、SR、FiniteGain的影响。通过改变以上参数的设置,可仿真各参数的影响,从而初步确定各参数。(相对于仿真结果需留出一定裕度)电路结构(1)第一积分器采用CDS结构抑制低频噪声和失调电压;开关尺寸需要在RC时间常数和电荷注入二者之间进行折中;运放采用两级结构,提高增益和摆幅,控制GBW和SR;输入信号和反馈信号共用输入电容,减小电容开销;CDS电容值不小于输入电容值;电路结构(2)第二积分器此级对整体性能影响不大,功能正确即可;电容取值较小;开关尺寸取最小;运放为折叠共源共栅结构;电路结构(3)比较器失调和噪声都会被环路抑制;采样率不高,因此速度要求也较低;磁滞电压达到整个输入范围的10%时对调制器的性能影响也不大。电路结构(
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