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基于FPGA的8*8点阵显示器的设计摘要:主要研究基于VHDL语言的8*8点阵显示汉字。首先对单个模块进行设计仿真调试,然后对整体模块的设计,通过编程、调试、仿真实现汉字的行扫描,其硬件系统下载正确的实现也获得了与软件仿真相吻合的结果。关键字:扫描分频点阵显示一.课题要求1.技术要求(1)EDA技术:EDA(ElectronicDesignAutomation)技术就是依赖功能强大的计算机,在EDA工具软件平台上,对以硬件描述语言HDL(HardwareDescriptionLanguage)为系统描述手段完成的设计文件,自动的完成逻辑编译、化简、分割、综合、布局布线以及逻辑优化和仿真测试,直至实现既定的电子线路系统功能。(2)VHDL语言:VHDL(Very--High--SpeedIntegratedCircuitHardwareDescriptionLanguage主要用于描述数字系统的结构,行为,功能和接口,除了含有许多硬件特征得语句外,VHDL的语言形式和描述风格与句法是十分类似于一般的计算机高级语言。(3)层次化设计:EDA设计一般采用自顶向下、由粗到细、逐步求精的方法。设计最顶层是指系统的整体要求,最下层是指具体的逻辑电路实现。自定向下是将数字系统的整体逐步分解为各个子系统和模块,若子系统规模较大则进一步分解为更小的子系统和模块,层层分解,直至整个系统中各子模块关系合理、便于实现为止。2.功能要求本次综合型数字电路课程设计组要完成点阵显示控制器的三种功能,分别是按键控制静态显示下一个字、汉字滚动和逐列显示(即先显示两边的各一列然后向外依次显示直至显示整个汉字,之后先显示中间的两行然后向外显示直至显示整个汉字),本次课程设计的所采用的软件是QuartersІІ6.0,硬件是EP2C5T144C8,通过对于8*8点阵显示相应的汉字,分别通过行和列控制显示。二.设计方案本次课程设计采用的是的行共阳列共阴的8*8点阵,因此不可能在同一时刻显示出整个汉字,为了显示出整个汉字,首先制作一个基本矩阵,然后按照时间的顺序进行逐行扫描,首先行给'00000001,同时列给相应的码值,第一行的的发光二极管就会有相应的亮,然后行给00000010,同时列给相应的码值,第二行的的发光二极管就会有相应的亮,用并行操作方式,如此周而复始的重复下去,根据人眼的视觉残留特性,使之形成整个汉字的显示。本次试验采用行扫描。图一.硬件总体框图三.单元模块设计仿真结果及分析1.选择输出模式libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycontrolisport(en:instd_logic;key:instd_logic_vector(1downto0);Q0,Q1,Q2:instd_logic_vector(7downto0);Y:outstd_logic_vector(7downto0));end;architectureex1ofcontrolisbeginprocess(en,key)beginifen='0'theny=11111111;elsecasekeyiswhen00=y=Q0;when01=y=Q1;when10=y=q2;whenothers=y=11111111;endcase;endif;endprocess;endex1;利用对输入按键的码值来控制显示:ENKey1Key0Y0XX11111111100Q0101Q1110Q211111111111仿真波形:通过仿真波形可以知道只有在EN=‘0’和开关都为高电平的情况下无显示,即输出都为高电平,其余情况下都会输出对应的码值。2.滚动显示滚动部分是将50MHZ时钟分为两个不同的频率,一个较快的时钟用来控制扫描的速度显示相应的汉字,一次从上向下逐行扫描,用一个较慢的时钟,当来了一个脉冲hang依次加1,就会有不同的码值输送给列,就会有汉字向上移一行。由于是行扫描在一定的时间里,即高频扫描每种输出的码值,使视觉上就可以实现向上滚动显示汉字的效果。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitygundongisport(clk:instd_logic;com:outstd_logic_vector(7downto0);red:outstd_logic_vector(7downto0));end;architectureex2ofgundongissignalst1:std_logic_vector(7downto0);signalosc,osd:std_logic;signald_ff:std_logic_vector(25downto0);signaldata,d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(7downto0);signalhang:std_logic_vector(6downto0);begincom=st1;red=data;d0=11000001whenhang=0000000else--周字第1行11010101whenhang=0000001else11000001whenhang=0000010else11000001whenhang=0000011else11000001whenhang=0000100else11000001whenhang=0000101else10111001whenhang=0000110else01111101whenhang=0000111else11111111whenhang=0001000else11101011whenhang=0001001else11001110whenhang=0001010else10010001whenhang=0001011else00000011whenhang=0001100else10001011whenhang=0001101else01011011whenhang=0001110else11010101whenhang=0001111else11001110whenhang=0010000else11111111whenhang=0010001else11111111;d1=11010101whenhang=0000000else11000001whenhang=0000001else11000001whenhang=0000010else11000001whenhang=0000011else11000001whenhang=0000100else10111001whenhang=0000101else01111101whenhang=0000110else11111111whenhang=0000111else11101011whenhang=0001000else11001110whenhang=0001001else10010001whenhang=0001010else00000011whenhang=0001011else10001011whenhang=0001100else01011011whenhang=0001101else11010101whenhang=0001110else11001110whenhang=0001111else11111111whenhang=0010000else11000001whenhang=0010001else--周字第1行11111111;d2=11000001whenhang=0000000else11000001whenhang=0000001else11000001whenhang=0000010else11000001whenhang=0000011else10111001whenhang=0000100else01111101whenhang=0000101else11111111whenhang=0000110else11101011whenhang=0000111else11001110whenhang=0001000else10010001whenhang=0001001else00000011whenhang=0001010else10001011whenhang=0001011else01011011whenhang=0001100else11010101whenhang=0001101else11001110whenhang=0001110else11111111whenhang=0001111else11000001whenhang=0010000else--周字第1行11010101whenhang=0010001else11111111;d3=11000001whenhang=0000000else11000001whenhang=0000001else11000001whenhang=0000010else10111001whenhang=0000011else01111101whenhang=0000100else11111111whenhang=0000101else11101011whenhang=0000110else11001110whenhang=0000111else10010001whenhang=0001000else00000011whenhang=0001001else10001011whenhang=0001010else01011011whenhang=0001011else11010101whenhang=0001100else11001110whenhang=0001101else11111111whenhang=0001110else11000001whenhang=0001111else--周字第1行11010101whenhang=0010000else11000001whenhang=0010001else11111111;d4=11000001whenhang=0000000else11000001whenhang=0000001else10111001whenhang=0000010else01111101whenhang=0000011else11111111whenhang=0000100else11101011whenhang=0000101else11001110whenhang=0000110else10010001whenhang=0000111else00000011whenhang=0001000else10001011whenhang=0001001else01011011whenhang=0001010else11010101whenhang=0001011else11001110whenhang=0001100else11111111whenhang=0001101else11000001whenhang=0001110else--周字第1行11010101whenhang=0001111else11000001whenhang=0010000else11000001whenhang=0010001else11111111;d5=11000001whenhang=0000000else10111001whenhang=0000001else01111101whenhang=0000010else11111111whenhang=0000011else11101011whenhang=0000100else11001110whenhang=0000101else10010001whenhang=0000110else00000011whenh
本文标题:基于FPGA的点阵显示控制器的设计
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